Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

中文翻译：

---

具有双重状态分配的基于LUT的Mealy FSM的改进特性

实际上，任何数字系统都包括顺序块。本文专门讨论用Mealy有限状态机（FSM）模型表示顺序块的情况。性能（最大工作频率）是FSM电路最重要的特性之一。在本文中，提出了一种方法，该方法旨在提高具有双重状态分配的基于LUT的Mealy FSM的工作频率。仅使用扩展状态代码即可完成此操作。这种方法允许排除将二进制状态码转换成扩展状态码的块。所提出的方法导致具有两个级别的逻辑块的基于LUT的Mealy FSM电路。任何逻辑电平的每个功能都由一个包含单个LUT的电路表示。所提出的方法通过一个合成示例进行了说明。使用标准基准进行的实验结果表明，与采用其他研究方法（Vivado的Auto和One-hot，JEDI，双重状态分配）生产的电路相比，所提出的方法生产的基于LUT的电路的工作频率明显更高。性能平均提高了15.9％至25.49％。与基于双重状态分配的电路相比，这些改进伴随着LUT数量的少量增长。与其他调查方法相比，我们的方法可提供最佳的时空产品。提议的方法的优点随着FSM输入和状态数量的增加而增加。