A novel mathematical approach has been proposed for input–output range extension of Pseudo-Taylor-Exponential-Approximation (PTEA) for achieving over seven-decade exponential function, while reducing the linearity error by 1 dB and attaining simple coefficients such as to realize this technique in designing the MOSFET based circuit. This new MPTEA technique, has been successfully utilized for its current-mode (I-I) CMOS implementation involving translinear principle of MOSFETs in weak inversion (WI) region. The CMOS synthesis procedure has been detailed and relevant second-order effects consists of noise, bulk-effect etc. have been explored. For post-layout simulations of the synthesized CMOS implementation, the SPECTRE simulation tool from Cadence, with 180 nM CMOS parameters, has been utilized to justify its practical workability. The proposition, in its CMOS layout, occupies an area of 0.0126mm² only. It consumes only ≈4.92 μW static power by utilizing ± 0.65 V power supply and produces 146.5 dB range of linear-in-dB output with ± 1 dB linearity error.

提出了一种新颖的数学方法来扩展伪泰勒指数逼近（PTEA）的输入-输出范围，以实现超过七个十年的指数函数，同时将线性误差降低1 dB并获得简单的系数，例如可以实现这一目标设计基于MOSFET的电路的技术。这项新的MPTEA技术已成功用于其电流模式（II）CMOS实现中，该实现涉及弱反转（WI）区域中MOSFET的跨线性原理。详细介绍了CMOS合成程序，并研究了相关的二阶效应，包括噪声，体效应等。对于合成CMOS实现的版图后仿真，来自Cadence的SPECTER仿真工具具有180 nM的CMOS参数，已被证明其实用性。仅^2个。通过使用±0.65 V电源，它仅消耗≈4.92μW静态功率，并产生146.5 dB的线性dB输出范围，线性误差为±1 dB。