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Development of a cost‐effective circuit hardware architecture for brushless direct current motor driver
International Journal of Circuit Theory and Applications ( IF 1.581 ) Pub Date : 2021-04-07 , DOI: 10.1002/cta.3011
Pratikanta Mishra, Atanu Banerjee, Mousam Ghosh, Sushanta Gogoi, Rukmi Dutta

A dual‐duty digital pulse‐width modulation (DDPWM) technique‐based cost‐effective control hardware architecture for brushless DC (BLDC) motor drive is reported in this paper. DDPWM control technique involves reduced computational complexity, which is beneficial in on‐chip area and power dissipation reduction. Simple Hall sensor‐based speed calculation and commutation circuits were also incorporated in the hardware to reduce the chip area further. The edge detection‐based speed calculation circuit was designed to be tolerant of any external noise or glitch in the Hall sensor signal. The proposed hardware architecture was implemented on the field‐programmable gate array (FPGA) and application‐specific integrated circuit (ASIC) platform using TSMC 180‐nm technology library. The ability of the integrated circuit (IC) for resource utilization reduction was validated by comparing the FPGA‐implemented architecture with the existing literature. The FPGA‐implemented architecture was also examined in real‐time using an experimental prototype BLDC motor setup. The drive response with dynamic load and speed variations, speed control precision, and glitch tolerant speed calculation is reported in the paper. The ASIC implementation demonstrates that the developed architecture sampled at 50 MHz is highly effective in the gate count and power dissipation reduction compared to the standard PI controller‐based width modulated pulse generation hardware architecture.

中文翻译:

为无刷直流电动机驱动器开发具有成本效益的电路硬件架构

本文报道了一种基于双占空比数字脉冲宽度调制(DDPWM)技术的经济高效的控制硬件架构,用于无刷直流(BLDC)电机驱动器。DDPWM控制技术可降低计算复杂度,这有利于降低片上面积并降低功耗。硬件中还集成了基于霍尔传感器的简单速度计算和换向电路,以进一步减小芯片面积。基于边缘检测的速度计算电路旨在容忍霍尔传感器信号中的任何外部噪声或干扰。拟议的硬件架构是使用TSMC 180纳米技术库在现场可编程门阵列(FPGA)和专用集成电路(ASIC)平台上实现的。通过将FPGA实现的架构与现有文献进行比较,验证了集成电路(IC)减少资源利用的能力。还使用实验原型BLDC电机设置对FPGA实现的架构进行了实时检查。本文报道了具有动态负载和速度变化,速度控制精度以及毛刺容许速度计算的驱动器响应。ASIC实现证明,与基于标准PI控制器的基于宽度调制的脉冲生成硬件架构相比,以50 MHz采样的已开发架构在门数和功耗降低方面非常有效。还使用实验原型BLDC电机设置对FPGA实现的架构进行了实时检查。本文报道了具有动态负载和速度变化,速度控制精度以及毛刺容许速度计算的驱动器响应。ASIC实现证明,与基于标准PI控制器的基于宽度调制的脉冲生成硬件架构相比,以50 MHz采样的已开发架构在门数和功耗降低方面非常有效。还使用实验原型BLDC电机设置对FPGA实现的架构进行了实时检查。本文报道了具有动态负载和速度变化,速度控制精度以及毛刺容许速度计算的驱动器响应。ASIC实现证明,与基于标准PI控制器的基于宽度调制的脉冲生成硬件架构相比,以50 MHz采样的已开发架构在门数和功耗降低方面非常有效。
更新日期:2021-04-08
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