In this work an evaluation of analog building blocks using junctionless nanowire transistors is presented. This analysis has been carried out through experimental measurements of junctionless nMOS transistors configured as two amplifier stages composed by single transistors, namely the common-source and the common-drain amplifiers. The performance of junctionless devices is evaluated as a function of channel length, nanowire width, doping concentration and bias condition, taking as figures of merit the voltage gain, linearity and, in the case of the common drain amplifier, the input voltage range. The obtained results indicate that these two basic analog blocks can be benefitted by the use of junctionless devices, providing nearly ideal voltage gain when configured as common-drain amplifier, and improvement on voltage gain and linearity with device narrowing in the case of the common-source amplifier.

中文翻译：

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论无结纳米线晶体管在基本模拟构建模块中的应用

在这项工作中，提出了使用无结纳米线晶体管对模拟构件的评估。通过对无结nMOS晶体管的实验测量进行了分析，该无结nMOS晶体管配置为由单个晶体管组成的两个放大器级，即共源极和共漏极放大器。无结器件的性能根据沟道长度，纳米线宽度，掺杂浓度和偏置条件的变化进行评估，以电压增益，线性度（对于普通漏极放大器而言）和输入电压范围为优值。获得的结果表明，使用无结器件可以使这两个基本模拟模块受益，当将其配置为共漏极放大器时，可以提供近乎理想的电压增益，