This paper proposes a well-optimized FPGA implementation of a chaos-based cryptosystem for real-time image encryption and decryption. A highly sensitive Pseudo-Random Number Generator (PRNG) based on the Lorenz chaotic system is designed to generate pseudo-random numbers. A high-quality encryption key is acquired by encrypting the numbers of a 128-bit counter using the PRNG. For image encryption, the image is first decomposed into 128-bit blocks. Then, the blocks are encrypted by XORing pixels with the key stream. R cycles of encryption can be achieved to increase complexity. Finally, the blocks are concatenated to form an encrypted image. The algorithm is designed, implemented, and validated on the Xilinx Zynq FPGA platform using the Vivado/System Generator tool. The hardware design is well optimized for pipeline processing and low resource utilization. The experimental synthesis indicates that the provided architecture achieves high performance in terms of frequency and throughput. The encryption scheme is evaluated and analyzed by several tools and tests using different images. The experimental simulation results demonstrate that the hardware implementation is faster than a software implementation while maintaining the technique’s effectiveness. The proposed hardware implementation is extremely adopted for secret image encryption and decryption that can be used in real-time applications.

中文翻译：

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Xilinx Zynq FPGA 用于硬件实现基于混沌的加密系统，用于实时图像保护

本文提出了一种优化的基于混沌密码系统的 FPGA 实现，用于实时图像加密和解密。基于 Lorenz 混沌系统的高灵敏度伪随机数生成器 (PRNG) 旨在生成伪随机数。通过使用 PRNG 对 128 位计数器的数字进行加密，获得高质量的加密密钥。对于图像加密，首先将图像分解为 128 位块。然后，通过将像素与密钥流进行异或来加密块。R可以实现加密循环以增加复杂性。最后，将这些块连接起来形成加密图像。该算法是使用 Vivado/System Generator 工具在 Xilinx Zynq FPGA 平台上设计、实现和验证的。硬件设计针对流水线处理和低资源利用率进行了很好的优化。实验综合表明，所提供的架构在频率和吞吐量方面实现了高性能。加密方案通过多种工具进行评估和分析，并使用不同的图像进行测试。实验仿真结果表明，硬件实现比软件实现更快，同时保持了技术的有效性。