The impact of variations in the donor and acceptor interface trap distributions on the fluctuation characteristics of 7-nm-node Si gate-all around n-nanowire FET (n-NWFETs) is analyzed in a hardware-calibrated quantum-corrected three-dimensional (3D) drift–diffusion (DD) numerical simulation framework. Shifting the energy position of the peak in the acceptor trap density distribution (D_it) induces greater surface potential fluctuations and carrier mobility degradation compared with variation of the donor traps. It is found that single-charge traps (SCTs) and random interface traps (RITs) induce larger V\(_{\text {T}}\) and drain-induced barrier lowering (DIBL) variations, along with charge neutrality level (CNL) variations induced by interface trap fluctuations. The Si n-NWFET shows better immunity to interface trap variability when the CNL is located between the midgap and the conduction-band edge. For future sub-7-nm high-performance NWFET logic devices, such interface trap variability will be one of the major sources of random fluctuations at the device level.

在硬件校准的量子校正的三维（）中分析了施主和受主界面陷阱分布的变化对n纳米线FET（n-NWFET）周围所有7 nm节点Si栅极的波动特性的影响。3D）漂移扩散（DD）数值模拟框架。与施主陷阱的变化相比，移动受体陷阱密度分布（D _it）中峰的能量位置_会引起更大的表面电势波动和载流子迁移率下降。发现单电荷陷阱（SCT）和随机接口陷阱（RIT）会产生较大的V \（_ {\ text {T}} \）漏极引起的势垒降低（DIBL）变化，以及界面陷阱波动引起的电荷中性能级（CNL）变化。当CNL位于中间能隙和导带边缘之间时，Si n -NWFET对界面陷阱可变性表现出更好的抗扰性。对于未来的7纳米以下高性能NWFET逻辑器件，这种接口陷阱可变性将是器件级随机波动的主要来源之一。