Cryptography systems have become inseparable parts of almost every communication device. Among cryptography algorithms, public-key cryptography, and in particular elliptic curve cryptography (ECC), has become the most dominant protocol at this time. In ECC systems, polynomial multiplication is considered to be the most slow and area consuming operation. This article proposes a novel hardware architecture for efficient field-programmable gate array (FPGA) implementation of Finite-field multipliers for ECC. Proposed hardware was implemented on different FPGA devices for various operand sizes, and performance parameters were determined. Comparing to state-of-the-art works, the proposed method resulted in a lower combinational delay and area–delay product indicating the efficiency of design.

中文翻译：

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用于FGPA的高效，高速，无重叠的基于Karatsuba的有限域乘法器

密码系统已成为几乎每个通信设备不可分割的部分。在密码算法中，公钥密码，尤其是椭圆曲线密码（ECC），已成为当前最主要的协议。在ECC系统中，多项式乘法被认为是最慢且最消耗区域的运算。本文提出了一种新颖的硬件体系结构，用于ECC的有限域乘法器的高效现场可编程门阵列（FPGA）实现。在不同的FPGA器件上针对各种操作数大小实现了建议的硬件，并确定了性能参数。与最新技术相比，所提出的方法产生了更低的组合延迟和面积延迟乘积，表明了设计的效率。