The electrostrictive 2-D field-effect transistor (EFET) is a steep-slope device that promises to offer aggressive length and voltage scalability. Two key features of this device are its high-drive strength with high ON–OFF current ratio and the isolated back-gate terminal, which provides us the fourth knob to control the transistor drive strength. The disadvantage of the technology is the increased device capacitance incurred due to the additional piezoelectric layer in the transistor structure. Second, although the back-gate biasing of EFETs provides us the fourth knob of control, statically biasing the back gate increases the static power consumption. Despite the idiosyncrasies of the technology, this work shows the use of EFETs in field-programmable gate arrays (FPGAs) to be advantageous because the added energy cost of device capacitance gets amortized by the improvement in performance and energy efficiency of using high-drive EFET transistors in the FPGA interconnect architecture. We also show that co-optimization of back-bias voltage along with transduction efficiency is essential in the FPGA subcircuit level for achieving an energy-efficient architecture. This work highlights the specific design approach tradeoffs that differ from prior CMOS approaches and provides guidance for the engineering parameters necessary for EFETs to evolve as a competitive technology.

中文翻译：

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使用电致伸缩2D FET在FPGA架构设计中的权衡评估

电致伸缩2D场效应晶体管（EFET）是一种陡峭的器件，有望提供出色的长度和电压可扩展性。该器件的两个关键特性是其高驱动强度和高ON-OFF电流比以及隔离的背栅端子，这为我们提供了用于控制晶体管驱动强度的第四个旋钮。该技术的缺点是由于晶体管结构中附加的压电层而导致器件电容增加。其次，尽管EFET的背栅偏置为我们提供了第四个控制旋钮，但是静态偏置背栅会增加静态功耗。尽管有这项技术的特殊性，这项工作表明，在现场可编程门阵列（FPGA）中使用EFET是有利的，因为通过在FPGA互连架构中使用高驱动EFET晶体管的性能和能效的提高，可以分摊设备电容的附加能源成本。我们还表明，在FPGA子电路级中，对反向偏置电压以及转换效率的共同优化对于实现节能架构至关重要。这项工作强调了与先前的CMOS方法不同的特定设计方法的权衡，并为EFET发展成为竞争技术所需的工程参数提供了指导。我们还表明，在FPGA子电路级中，对反向偏置电压以及转换效率的共同优化对于实现节能架构至关重要。这项工作强调了与先前的CMOS方法不同的特定设计方法的权衡，并为EFET发展成为竞争技术所需的工程参数提供了指导。我们还表明，在FPGA子电路级中，对反向偏置电压以及转换效率的共同优化对于实现节能架构至关重要。这项工作强调了与先前的CMOS方法不同的特定设计方法的权衡，并为EFET发展成为竞争技术所需的工程参数提供了指导。