This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor limiting the sample speed under ultra-low voltages. Delayed cross-coupling comparator is introduced in this work, which enhances the comparator regeneration while keeping the noise comparable. A 0.35V 8b 12MS/s SAR ADC is designed in a 65nm CMOS technology to prove the proposed techniques. The post-layout simulated SAR ADC consumes only $6.71~\mu \text{W}$ and achieves SNDR of 48.8dB at Nyquist input, resulting in a figure-of-merit (FoM) of 2.47 fJ/convertion-step. Simulation results show the proposed speed-enhancement techniques improve the sampling rate of SAR ADC significantly under near-threshold supply voltages.

中文翻译：

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近阈值SAR ADC的采样和比较器速度增强技术

本文介绍了在接近阈值电源电压的情况下，SAR ADC的采样和比较器速度增强技术。所提出的电平移位升压电路为采样时钟产生尖锐的下降沿，这是限制超低电压下采样速度的关键因素。在这项工作中引入了延迟交叉耦合比较器，它可以在保持噪声可比的同时，提高比较器的再生能力。在65nm CMOS技术中设计了0.35V 8b 12MS / s SAR ADC，以证明所提出的技术。布局后模拟SAR ADC仅消耗 $ 6.71〜\ mu \ text {W} $ 并在奈奎斯特输入端实现48.8dB的SNDR，因此品质因数（FoM）为2.47 fJ /转换步长。仿真结果表明，所提出的速度增强技术可在接近阈值电源电压的情况下显着提高SAR ADC的采样率。