ABSTRACT

Advanced CMOS technology is highly susceptible to ageing effects such as negative bias temperature instability (NBTI) and process variability. This article focuses on investigating the ‘combined impact’ of NBTI degradation along with the process, voltage and temperature (PVT) variations on SRAM metrics. These issues impact the performance of SRAM (Static Random Access Memory) cell in many ways but the two main dynamic metrics are critical read-stability and write-ability. The dynamic metrics can, in turn, be characterised by their static metrics, that determine the static noise margins (SNM) of SRAM. The dynamic metrics were analysed for symmetric and asymmetric NBTI degradation of two inverters of SRAM. NBTI degradations were incorporated on the pull-up transistors of SRAM cell. Furthermore, results of the correlated performance metrics are presented for varied data storage patterns in SRAM cell over its lifetime. This analysis aims to provide an insight into the effects of integrated PVT and NBTI degradation on SRAM cell performance, enabling robust designs and help designers at the early stage of design to mitigate system failure.

摘要

先进的 CMOS 技术极易受到老化效应的影响，例如负偏置温度不稳定性 (NBTI) 和工艺可变性。本文重点研究 NBTI 退化与工艺、电压和温度 (PVT) 变化对 SRAM 指标的“综合影响”。这些问题以多种方式影响 SRAM（静态随机存取存储器）单元的性能，但两个主要的动态指标是关键的读取稳定性和写入能力。反过来，动态度量可以通过它们的静态度量来表征，这些静态度量决定了 SRAM 的静态噪声容限 (SNM)。分析了 SRAM 的两个反相器的对称和非对称 NBTI 退化的动态指标。NBTI 退化被纳入 SRAM 单元的上拉晶体管。此外，给出了 SRAM 单元在其生命周期内不同数据存储模式的相关性能指标的结果。该分析旨在深入了解集成 PVT 和 NBTI 退化对 SRAM 单元性能的影响，从而实现稳健的设计，并帮助设计人员在设计的早期阶段减少系统故障。