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The Design Process for Google's Training Chips: TPUv2 and TPUv3
IEEE Micro ( IF 3.6 ) Pub Date : 2021-02-09 , DOI: 10.1109/mm.2021.3058217
Thomas Norrie 1 , Nishant Patil 1 , Doe Hyun Yoon 1 , George Kurian 1 , Sheng Li 1 , James Laudon 1 , Cliff Young 1 , Norman Jouppi 1 , David Patterson 2
Affiliation  

Five years ago, few would have predicted that a software company like Google would build its own computers. Nevertheless, Google has been deploying computers for machine learning (ML) training since 2017, powering key Google services. These Tensor Processing Units (TPUs) are composed of chips, systems, and software, all co-designed in-house. In this paper, we detail the circumstances that led to this outcome, the challenges and opportunities observed, the approach taken for the chips, a quick review of performance, and finally a retrospective on the results. A companion paper describes the supercomputers built from these chips, the compiler, and a detailed performance analysis [Jou20].

中文翻译:

Google培训芯片的设计流程:TPUv2和TPUv3

五年前,很少有人会预测像谷歌这样的软件公司会建造自己的计算机。尽管如此,自2017年以来,谷歌一直在部署用于机器学习(ML)培训的计算机,以支持关键的Google服务。这些张量处理单元(TPU)由芯片,系统和软件组成,所有这些均由内部共同设计。在本文中,我们详细介绍了导致这一结果的情况,所观察到的挑战和机遇,采用筹码的方法,对性能的快速回顾以及对结果的回顾。随附的论文描述了由这些芯片构建的超级计算机,编译器以及详细的性能分析[Jou20]。
更新日期:2021-03-30
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