Purpose

Reference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.

Design/methodology/approach

This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.

Findings

The post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.

Research limitations/implications

Slew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.

Practical implications

Reference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.

Social implications

BGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.

Originality/value

FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

中文翻译：

---

折叠式共源共栅运放设计及其应用——带隙参考电路

目的

参考电压或电流发生器是模拟或数字电路设计的重要要求。带隙参考电路 (BGR) 是生成参考电压的最常见方法。本文旨在提供折叠共源共栅运算放大器（FC 运算放大器）和 BGR 电路设计的详细见解。讨论了 180 nm 半导体实验室 (SCL) 工艺中从设计到电路布局的完整研究流程，最终形成可能流片的键合图。这项研究工作得到了 MeitY、Govt 的支持。印度，通过特殊人力开发项目从芯片到系统设计。

设计/方法论/途径

本文提供了 FC 运算放大器和 BGR 电路设计的详细见解。讨论了 180 nm SCL 工艺上两个电路从设计到布局的完整研究流程，最终形成了可能流片的键合图。第 2 部分展示了 FC 运算放大器、β 乘法器电路的设计及其仿真结果。第 3 节描述了传统 BGR 的设计和所提出的 BGR 与其他最先进的 BGR 电路的比较。第 4 节给出了它们的性能比较。结论在第 5 节中给出。

发现

FC 运算放大器的布局后仿真显示开环增益为 64.5 dB、3 dB 频率为 5.5 KHz、单位增益带宽为 8.7 MHz、压摆率为 8.4 V/μs 、 CMRR 为 111 dB 以及功率25.5μW。在这两种 BGR 设计中，传统 BGR 产生 693 mV 参考电压，温度系数为 16 ppm/°C，另一种采用曲率校正的 BGR 产生 1.3 V 参考电压，温度系数为 6.3 ppm/°C，两者结果温度范围为−40°C 至 125°C。采用 180 nm SCL 工艺设计的电路芯片布局可确保设计规则检查 (DRC)、天线和布局与原理图 (LVS) 与金属填充的清洁。

研究局限性/影响

转换速率、稳定性分析、功率是为 BGR 设计运算放大器时应注意的重要参数。直流增益应保持较高以减少失调误差。输入共模范围由工作温度范围决定。较高的电源抑制比将降低 BGR 对电源电压变化的敏感性。输入偏移应保持较低，以减少参考电压中的 BGR 误差。然而，本文强调使用仿真工具从原理图到布局的流程。作为研究的一部分，还探讨了在给定的带密封环的 SCL 框架尺寸中 BGR 和 FC 设计流片的粘合图，以实现可能的流片。

实际影响

参考电压或电流发生器是模拟或数字电路设计的重要要求。BGR 是生成参考电压的最常见方式。本文提供了 FC 运算放大器和 BGR 电路设计的详细见解。讨论了 180 nm SCL 工艺上从设计到电路布局的完整研究流程，最终形成了可能流片的键合图。电路的芯片布局采用 180 nm SCL 工艺设计，确保使用 Cadence virtuoso 和 Mentor Graphics Calibre 仿真工具通过金属填充实现 DRC、天线和 LVS 清洁。

社会影响

BGR 是生成参考电压的最常见方式。本文详细介绍了使用折叠共源共栅运算放大器的 BGR 设计。FC 运算放大器使用 beta 乘法器电路和高摆幅共源共栅电流镜电路进行偏置。本文讨论了从原理图到布局的 FC 电路设计流程。

原创性/价值

FC 运算放大器使用 beta 乘法器电路和高摆幅共源共栅电流镜进行偏置。本文讨论了从原理图到布局的 FC 设计流程。该电路采用 180 nm SCL 技术和 1.8 V 电源设计。布局后仿真显示开环增益为 64.5 dB，3 dB 频率为 5.5 KHz，单位增益带宽为 8.7 MHz，压摆率为 8.4 V/μs，CMRR 为 111 dB，功率为 25.5 µW。BGR 使用 FC 运算放大器进行设计。在原理图仿真中，所提出的 BGR 在 -40°C 至 125°C 范围内产生 1.3 V 参考电压，温度系数为 6.3 ppm/°C。