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Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-01-01 , DOI: 10.1109/jssc.2020.3039800
Masanori Natsui , Akira Tamakoshi , Hiroaki Honjo , Toshinari Watanabe , Takashi Nasuno , Chaoliang Zhang , Takaho Tanigawa , Hirofumi Inoue , Masaaki Niwa , Toru Yoshiduka , Yasuo Noguchi , Mitsuo Yasuhira , Yitao Ma , Hui Shen , Shunsuke Fukami , Hideo Sato , Shoji Ikeda , Hideo Ohno , Tetsuo Endoh , Takahiro Hanyu

The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has become new technology platform to overcome the issue in power consumption of logic for the application from IoT to AI; however, STT-MRAM has a tradeoff relationship between endurance, retention, and access time. This is because the MTJ device used in STT-MRAM is a two-terminal device, and excessive read current for high-speed readout can cause unexpected data writing, or so-called read disturbance. In order to meet the demand for the realization of high-speed nonvolatile memory, the development of new memories based on innovative circuit, device, and integration process is required. In this article, we demonstrate an SOT-MRAM, a nonvolatile memory using MTJ devices with spin-orbit-torque (SOT) switching that have a read-disturbance-free characteristic. The SOT-MRAM fabricated using a 55-nm CMOS process is implemented in a dual-port configuration utilizing a three-terminal structure of the device for realizing a wide bandwidth applicable to high-speed applications. In addition, a read-energy reduction technique called a self-termination scheme is also implemented. Through the measurement results of the fabricated prototype chip, we will demonstrate the proposed SOT-MRAM achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under a magnetic-field-free condition.

中文翻译:

双端口 SOT-MRAM 在无现场辅助条件下实现 90-MHz 读取和 60-MHz 写入操作

使用新兴的非易失性器件开发新的功能性存储器已被广泛研究。自旋转移矩磁阻随机存取存储器(STT-MRAM)已成为克服从物联网到人工智能应用逻辑功耗问题的新技术平台;然而,STT-MRAM 在耐用性、保留和访问时间之间具有权衡关系。这是因为 STT-MRAM 中使用的 MTJ 器件是一个两端器件,高速读出的过大读取电流会导致意外的数据写入,即所谓的读取干扰。为了满足实现高速非易失性存储器的需求,需要开发基于创新电路、器件和集成工艺的新型存储器。在本文中,我们演示了 SOT-MRAM,使用具有自旋轨道扭矩 (SOT) 开关的 MTJ 器件的非易失性存储器,具有无读取干扰特性。使用 55-nm CMOS 工艺制造的 SOT-MRAM 在双端口配置中实现,利用器件的三端子结构实现适用于高速应用的宽带宽。此外,还实施了称为自终止方案的读取能量减少技术。通过制造的原型芯片的测量结果,我们将证明所提出的 SOT-MRAM 在无磁场条件下以 1.2V 电源电压实现 60MHz 写入和 90MHz 读取操作。使用 55-nm CMOS 工艺制造的 SOT-MRAM 在双端口配置中实现,利用器件的三端子结构实现适用于高速应用的宽带宽。此外,还实施了称为自终止方案的读取能量减少技术。通过制造的原型芯片的测量结果,我们将证明所提出的 SOT-MRAM 在无磁场条件下以 1.2V 电源电压实现 60MHz 写入和 90MHz 读取操作。使用 55-nm CMOS 工艺制造的 SOT-MRAM 在双端口配置中实现,利用器件的三端子结构实现适用于高速应用的宽带宽。此外,还实施了称为自终止方案的读取能量减少技术。通过制造的原型芯片的测量结果,我们将证明所提出的 SOT-MRAM 在无磁场条件下以 1.2V 电源电压实现 60MHz 写入和 90MHz 读取操作。
更新日期:2020-01-01
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