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A Single-Trim Switched Capacitor CMOS Bandgap Reference With a 3σ Inaccuracy of +0.02%, −0.12% for Battery-Monitoring Applications
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2020-12-30 , DOI: 10.1109/jssc.2020.3044165
Jun-Ho Boo , Kang-Il Cho , Ho-Jin Kim , Jae-Geun Lim , Yong-Sik Kwak , Seung-Hoon Lee , Gil-Cho Ahn

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, $\beta $ -compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( $\beta $ ), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a $\beta $ of about 2.7 at 27 °C in a 0.18- $\mu \text{m}$ CMOS process. The proposed SC BGR achieves a $3\sigma $ inaccuracy of +0.02%, −0.12% from −40 °C to 125 °C. From a 1.8-V supply voltage, it consumes $17~\mu \text{A}$ at 27 °C and occupies an active area of 0.38 mm 2 .

中文翻译:

具有3的单边缘开关电容器CMOS带隙基准σ 电池监视应用中的+0.02%,-0.12%的不准确度

本文介绍了一种用于电池监控应用的单修剪开关电容器(SC)CMOS带隙基准(BGR)。对于单温度修整, $ \ beta $ 补偿和曲率校正技术用于最小化非比例绝对温度(PTAT)误差。结合这些技术,本文提出了一种具有低通滤波的动态元素匹配(DEM)技术,该技术在数字域中采用了delta-sigma模数转换器(ADC)的抽取滤波器。它可以进一步减少由偏置电流,PNP晶体管电流增益( $ \ beta $ )和SC求和放大器中的增益系数。剩余的PTAT错误可通过单次室温修整来消除。带隙电路是使用垂直PNP晶体管实现的,该晶体管具有 $ \ beta $ 在0.18- $ \ mu \ text {m} $ CMOS工艺。拟议的SC BGR实现了 $ 3 \ sigma $ 从−40°C至125°C的误差为+0.02%,-0.12%。从1.8V电源电压消耗 $ 17〜\ mu \ text {A} $ 在27°C时,其有效面积为0.38 mm 2
更新日期:2020-12-30
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