This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL) that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with adopting a traditional time-to-digital converter (TDC), which relies on gate delay in the time domain, power-efficient quantization of PE by the proposed conversion scheme in the FDV domain can be accomplished with a higher power-supply/common-mode rejection ratio (PSRR/CMRR), lower process, voltage, and temperature (PVT) sensitivity, finer resolution, and better linearity. The implemented DPLL covers the fractional-N operation by a 10-bit differential current digital-to-analog converter (DAC) with a resistive load to represent the fractional phase/time. A differential $dv/dt$ ramp is employed to linearly transfer the preset initial voltage into a small phase/voltage error, which is digitized by a narrow-range fine-resolution 7-bit self-timed successive-approximation-register analog-to-digital converter (SAR-ADC). The prototype DPLL, implemented in 130-nm CMOS, achieves 101-fs rms jitter, integrated from 10 kHz to 40 MHz, in the fractional-N mode with sub-12-bit fractional-frequency-control words, using an 80-MHz reference clock (REF), consuming 9.2 mW. This corresponds to a figure of merit (FoM) of −250.3 dB. The measured worst case fractional spur level is −56 dBc.

中文翻译：

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在全差分电压域中量化相位误差的高效功率小数N DPLL

本文提出了一种高功率效率的低抖动小数N分频数字锁相环（DPLL），该锁相环解决了全差分电压（FDV）域中的相位误差（PE）。与采用依赖时域门延迟的传统时间数字转换器（TDC）相比，通过建议的转换方案在FDV域中对PE进行功率有效的量化可以实现更高的电源/共模抑制比（PSRR / CMRR），更低的工艺，电压和温度（PVT）灵敏度，更精细的分辨率以及更好的线性度。已实现的DPLL通过具有电阻负载的10位差分电流数模转换器（DAC）覆盖小数N运算，以表示小数相位/时间。差异 $ dv / dt $ 斜坡用于将预设的初始电压线性转换为较小的相位/电压误差，该误差通过窄范围的高分辨率7位自定时逐次逼近寄存器模数转换器（SAR-ADC）进行数字化）。DPLL原型以130nm CMOS实现，在小数N模式下使用12MHz的分数频率控制字以80MHz的频率实现了101fs rms抖动，在10kHz至40MHz范围内集成。参考时钟（REF），消耗9.2 mW。这对应于-250.3 dB的品质因数（FoM）。测得的最坏情况分数杂散电平为-56 dBc。