This article describes a 4 $\times $ 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain–BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e−5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.

中文翻译：

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7nm FinFET中基于ADC-DSP的10至112-Gb / s多标准接收器

本文介绍了4 $ \次$ 针对长距离（LR）通道的112 Gb / s数字接收器。提出了一种SNR优化方法，该方法在不牺牲BER的情况下放宽了ADC分辨率要求和FFE抽头的数量。离散时间前端克服了增益带宽限制，在28 GHz频率下可提供10+ dB的增益。然后，一个56 GS / s ADC将信号转换为仅消耗195 mW的6位数字。以下基于DFE-FFE的数字均衡器能够补偿36dB的损耗，实现BER为2e-5。此外，基于TDC和ISI滤波器的低延迟时序恢复可在10到112 Gb / s的广泛数据速率（包括28 Gb / s NRZ）上满足抖动容限规范。整个接收器功耗为338 mW，能量效率为3.18pJ / bit。