A ferroelectric based electrostatic doping (Fe-ED) technique is proposed, as the alternative to chemical doping, providing non-volatile and programmable free electrons and holes for nanoscale devices. We show that Fe-ED achieves non-volatility and reconfigurability via the ferroelectric film inserted into the polarity gate, producing the reconfigurable nanosheet FETs (NSFETs) without the requirement of a constant bias. Thanks to the naturally formed lightly doped drain structures and the extremely high doping concentration over $1\times 10^{21}$ cm ⁻³ in source/drain (S/D) regions, Fe-ED NSFETs exhibit the promising potential benefits for device scaling including the improved subthreshold swing, the suppressed drain-induced barrier lowering, and the ultralow S/D region resistance. Our study suggests a promising doping strategy of Fe-ED for versatile reconfigurable nanoscale transistors and highly integrated circuits.

中文翻译：

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纳米器件中铁电基静电掺杂的建议

提出了一种基于铁电的静电掺杂（Fe-ED）技术，作为化学掺杂的替代方法，它为纳米级器件提供了非易失性和可编程的自由电子和空穴。我们表明，Fe-ED通过插入极性门中的铁电薄膜实现了非挥发性和可重构性，从而产生了可重构纳米片FET（NSFET），而无需恒定偏置。归功于自然形成的轻掺杂漏极结构以及超高的掺杂浓度 $ 1 \乘以10 ^ {21} $ 在源极/漏极（S / D）区的cm ^-3处，Fe-ED NSFET展现出了有望实现器件缩放的潜在优势，包括改善了亚阈值摆幅，抑制了漏极引起的势垒降低以及超低的S / D区电阻。我们的研究表明，对于通用的可重构纳米级晶体管和高度集成电路，Fe-ED的掺杂策略很有希望。