In this article, we investigate the occurrence of defects in integrated circuit fabrication and show how spatial analysis can be effective in grasping and representing spatial regularities in defect patterns on the silicon supports, called wafers, used to produce microchips. Defects occurring on the wafer surface are the main cause of yield loss in the semiconductor industry; hence, to promptly detect an excess of defects and identify their spatial structure is crucial to the entire fabrication process. To address this hard-to-solve problem, this article proposes a concatenation of different methods, namely, a control chart, a clustering algorithm, and a graphical tool. First, a control chart based on the p-value of an appropriate test recognizes spatially structured defects on the wafer area. Then a clustering procedure grounded on the minimum spanning tree algorithm is adopted to identify those regions more prone to defect occurrences. Finally, alpha-shapes are employed to display their shape effectively. The suggested procedure proves to be extremely fast and effective, allowing its implementation in-line during the fabrication process. This provides a great advantage in modern microelectronics where items tend to be highly specialized and often produced in small lots. In particular, due to the Monte Carlo nature of the procedure, the control chart proposed hereafter does not require gold standard data to be set. This is particularly advantageous for small lot production, which is typically limited in time and does not permit to collect long time series of the charting statistics.

中文翻译：

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半导体制造中空间缺陷的识别

在本文中，我们研究了集成电路制造中缺陷的发生，并展示了空间分析如何有效地掌握和表示用于生产微芯片的硅支撑（称为晶片）上的缺陷图案的空间规律。晶圆表面出现的缺陷是半导体行业良率下降的主要原因；因此，及时检测过量缺陷并识别其空间结构对整个制造过程至关重要。为了解决这个难以解决的问题，本文提出了不同方法的串联，即控制图、聚类算法和图形工具。一、基于p的控制图- 适当测试的值识别晶片区域上的空间结构缺陷。然后采用基于最小生成树算法的聚类程序来识别那些更容易出现缺陷的区域。最后，使用 alpha 形状来有效地显示它们的形状。事实证明，建议的程序非常快速和有效，允许在制造过程中在线实施。这为现代微电子产品提供了巨大的优势，因为现代微电子产品往往高度专业化并且通常小批量生产。特别是，由于程序的蒙特卡罗性质，下文提出的控制图不需要设置黄金标准数据。这对于小批量生产特别有利，