A novel energy-saving and area-efficient tri-level switching scheme is proposed for successive approximation register analog-to-digital converters (SAR ADCs). Different from most published tri-level switching schemes, a new third reference voltage V_aq which equals to 1/4 V_ref is applied to the proposed scheme. And benefiting from V_aq, the proposed scheme achieves 87.5% capacitor area reduction over the conventional scheme. Due to the capacitor-splitting structure and top-plate sampling, the switching energy is negative during the first three switching cycles, which means the capacitor arrays return energy back to the reference voltages and results in significant energy saving. For a 10-bit SAR ADC, the average switching energy of proposed scheme is only 5.3 \(CV_{{{\text{ref}}}}^{2}\), which realizes 99.61% energy saving compared with the conventional scheme. Moreover, the proposed scheme is of low control logic complexity since single-side switching is applied during the remaining switching cycles. Therefore, the proposed scheme achieves a good trade-off among energy saving, area efficiency and logic complexity. For a 10-bit SAR ADC, the simulated differential nonlinearity (DNL) and integral nonlinearity (INL) with 1% capacitor mismatch are 0.322 LSB and 0.321 LSB, respectively. Considering 0.3% reference voltage mismatch, the mean values of effective number of bits (ENOB), signal-to-noise-and-distortion ratio (SNDR) and spurious-free-dynamic-range (SFDR) are 9.77 bit, 60.57 dB and 75.43 dB, respectively, through 500 Monte Carlo simulations. To verify the feasibility of circuit implementation, transistor level simulation of a 0.6-V 10-bit 200-KS/s SAR ADC in 40-nm CMOS technology is performed. The ENOB, SNDR and SFDR of SAR ADC with 98.83-kHz Nyquist rate input are 9.66 bit, 59.90 dB and 71.98 dB, respectively.

针对逐次逼近寄存器模数转换器（SAR ADC），提出了一种新颖的节能高效的三电平开关方案。与大多数公开的三电平开关方案不同，将等于1/4 V _ref的新的第三参考电压V _aq应用于建议的方案。并受益于V _aq与传统方案相比，该方案可将电容器面积减少87.5％。由于采用了电容器分离结构和顶板采样，因此在前三个开关周期中开关能量为负，这意味着电容器阵列将能量返回到参考电压，从而显着节省了能量。对于10位SAR ADC，建议方案的平均开关能量仅为5.3 \（CV _ {{{\ text {ref}}}} ^ {2} \）与传统方案相比，可实现99.61％的节能。此外，由于在剩余的开关周期中应用了单侧开关，因此所提出的方案具有较低的控制逻辑复杂度。因此，所提出的方案在节能，面积效率和逻辑复杂度之间取得了良好的折衷。对于10位SAR ADC，电容器失配为1％时的模拟差分非线性（DNL）和积分非线性（INL）分别为0.322 LSB和0.321 LSB。考虑到0.3％的参考电压失配，有效位数（ENOB），信噪比和失真比（SNDR）和无杂散动态范围（SFDR）的平均值分别为9.77位，60.57 dB和通过500次蒙特卡洛模拟分别为75.43 dB。为了验证电路实施的可行性，在40-nm CMOS技术中对0.6-V 10位200-KS / s SAR ADC进行了晶体管级仿真。具有98.83 kHz奈奎斯特速率输入的SAR ADC的ENOB，SNDR和SFDR分别为9.66位，59.90 dB和71.98 dB。