The time-interleaved analog-to-digital converter has shown to be a key component of the latest ultra-wide band systems. Unfortunately, the sub-analog-to-digital converters are prone to parameter deviations caused by process-voltage-temperature, which can affect the output linearity. This article presents a foreground time-interleaved analog-to-digital converter mismatch calibration, which is one of the few available in the literature that can be adapted to any interleaving factor and calibrate overall frequency-dependent mismatches. Moreover, the proposed scheme is highly suited to state-of-the-art transceivers without the need for extra analog expensive circuitry or input signal purity. The foreground signal and correction structure complexity are greatly alleviated due to the developed mismatch detection and genetic algorithm logic. Numerical simulations and measurement results are presented. A commercial 3.6-GS/s time-interleaved analog-to-digital converter was utilized to verify the algorithm performance and experimental issues regarding mixed mismatches are addressed.

中文翻译：

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基于遗传算法的M通道时间交错模数转换器的前景校准

时间交错的模数转换器已被证明是最新超宽带系统的关键组成部分。不幸的是，子模数转换器易于产生由过程电压-温度引起的参数偏差，这会影响输出线性度。本文介绍了前景时间交错的模数转换器失配校准，这是文献中为数不多的可用于适应任何交织因子并校准总体频率相关失配的校准之一。此外，提出的方案非常适合最新的收发器，而无需额外的昂贵的模拟电路或输入信号纯度。由于开发了失配检测和遗传算法逻辑，大大降低了前景信号和校正结构的复杂性。给出了数值模拟和测量结果。利用商用的3.6 GS / s时间交错式模数转换器来验证算法性能，并解决了有关混合失配的实验问题。