A 6-bit 2.3 GS/s single-channel sub-radix pipeline ADC using an incomplete settling concept is presented. A radix detector is proposed to detect stage gain in the background so that low gain and low bandwidth opamps can be utilized to conserve power. The raw ADC output codes can be reconstructed with the detected radix to retrieve its accuracy. The simulated results show that the prototype ADC in 40 nm CMOS process exhibits an SNDR of 34.3 dB at Nyquist input frequency with the conversion rate of 2.3 GS/s. It consumes 94 mW at 1 V supply and occupies an active chip area of 0.12 mm².

中文翻译：

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使用不完整建立技术和背景基数检测器的34.3 dB SNDR，2.3GS / s子基数管线ADC

提出了一种使用不完整建立概念的6位2.3 GS / s单通道子基数流水线ADC。提出了一种基数检测器来检测背景中的级增益，以便可以利用低增益和低带宽运算放大器来节省功率。原始ADC输出代码可以用检测到的基数重建，以恢复其精度。仿真结果表明，采用40 nm CMOS工艺的原型ADC在Nyquist输入频率下的SNDR为34.3 dB，转换速率为2.3 GS / s。在1 V电源下消耗的功率为94 mW，占用的有源芯片面积为0.12 mm ²。