In this paper we propose an efficient approach to design fractional-order elements’ (FOEs) series, while using a very limited set of “seed” FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order \(\alpha \) being in the range \([-2,2]\). The proposed circuit may simply be extended to design fractional-order elements from wider range of \(\alpha \) to follow designers’ requirements. To show the efficiency of the described technique, the use of only up to two “seed” FOEs with properly selected fractional order \(\alpha _\mathrm {seed}\) as passive elements results in the design of a series of 17 FOEs with different \(\alpha \) being in the range \([-2,2]\). Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.

在本文中，我们提出了一种设计分数阶元素（FOE）系列的有效方法，同时使用了非常有限的一组“种子” FOE。所提出的方法遵循通用的阻抗变换器/变换器的思想，然而，也提出了一种采用运算跨导放大器的合适电路解决方案，该解决方案可用于分数阶\（\ alpha \）在范围\内的接地FOE的设计。（[-2,2] \）。所提出的电路可以简单地扩展为设计\（\ alpha \）范围更广的分数阶元素，以符合设计人员的要求。为了显示所描述的技术的效率，利用最多只与适当选择的分数阶两个“种子”的敌人\（\阿尔法_ \ mathrm {种子} \）作为无源元件，将设计出一系列17个FOE，而不同的\（\ alpha \）处于\（[-2,2] \）范围内。提出了Cadence布局后的仿真结果，证明了我们设计理念的可操作性和鲁棒性。还提出了基本的分数1.75阶低通滤波器，以显示所提出的GIC正在实施的FOE的利用。