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Experimental Body-input Three-stage DC offset Calibration Scheme for Memristive Crossbar
arXiv - CS - Emerging Technologies Pub Date : 2021-03-03 , DOI: arxiv-2103.02651
Charanraj Mohan, L. A. Camuñas-Mesa, Elisa Vianello, Carlo Reita, José M. de la Rosa, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco

Reading several ReRAMs simultaneously in a neuromorphic circuit increases power consumption and limits scalability. Applying small inference read pulses is a vain attempt when offset voltages of the read-out circuit are decisively more. This paper presents an experimental validation of a three-stage calibration scheme to calibrate the DC offset voltage across the rows of the memristive crossbar. The proposed method is based on biasing the body terminal of one of the differential pair MOSFETs of the buffer through a series of cascaded resistor banks arranged in three stages: coarse, fine and finer stages. The circuit is designed in a 130 nm CMOS technology, where the OxRAM-based binary memristors are built on top of it. A dedicated PCB and other auxiliary boards have been designed for testing the chip. Experimental results validate the presented approach, which is only limited by mismatch and electrical noise.

中文翻译:

忆阻纵横开关的实验人体输入三阶段直流偏移校准方案

在神经形态电路中同时读取多个ReRAM会增加功耗并限制可扩展性。当读出电路的失调电压决定性地更大时,施加小的推断读脉冲是徒劳的。本文介绍了一种三阶段校准方案的实验验证,该方案用于校准忆阻交叉开关各行之间的直流偏移电压。所提出的方法是基于通过一系列分三级排列的级联电阻器组对缓冲器的一个差分对MOSFET中的一个MOSFET的本体端子进行偏置的:粗级,精级和精级。该电路采用130 nm CMOS技术设计,其中基于OxRAM的二进制忆阻器构建在该电路之上。已经设计了专用的PCB和其他辅助板来测试芯片。
更新日期:2021-03-05
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