High-Level Synthesis (HLS) tools help engineers to deal with the complexity of building heterogeneous embedded systems that make it use of reconfigurable technology. Also, HLS opens up a way for introducing, into the development flow of custom hardware components, techniques well known in the software industry such as Test-Driven Development (TDD). However, the support provided by HLS tools for verification activities is limited, and it is usually focused on the initial steps of the design process. In this paper, a hardware testing framework is introduced as an enabler for effortless on-board verification of components by applying the Unit Testing Paradigm and, hence, realizing TDD on reconfigurable hardware. The proposed solution comprises a hardware/software introspection infrastructure to verify modules of a system at different stages, spawning multiple abstraction levels without extra effort nor redesigning the component. Our solution has been implemented for the Xilinx ZynQ FPGA-SoC architecture and applied to the verification of C-kernels within the CHStone Benchmark. Effortless integration into the Xilinx Vivado design flow and tools is supported by a set of automatic generation scripts developed for this end. Experimental results show a considerable speedup of the verification time and unveils inaccuracies concerning the co-simulation estimation obtained by Xilinx tools when compared with the on-board latency measured by our framework.

中文翻译：

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面向跨抽象级别的基于FPGA的模块的测试驱动开发

高级综合（HLS）工具可帮助工程师应对使用可重配置技术构建异构嵌入式系统的复杂性。此外，HLS还为将自定义硬件组件的开发流程引入软件行业中众所周知的技术（例如测试驱动开发（TDD））开辟了一条途径。但是，HLS工具为验证活动提供的支持是有限的，并且通常集中在设计过程的初始步骤上。在本文中，引入了硬件测试框架，作为通过应用单元测试范式毫不费力地对组件进行车载验证的引擎，从而在可重配置的硬件上实现TDD。所提出的解决方案包括硬件/软件自省基础结构，以在不同阶段验证系统的模块，无需额外的努力也无需重新设计组件即可产生多个抽象级别。我们的解决方案已针对Xilinx ZynQ FPGA-SoC架构实施，并已应用于CHStone Benchmark中的C内核验证。为此目的而开发的一组自动生成脚本支持轻松集成到Xilinx Vivado设计流程和工具中。实验结果表明，验证时间显着加快，并且与通过我们的框架测得的板上延迟相比，Xilinx工具获得的协同仿真估计存在不准确之处。为此目的而开发的一组自动生成脚本支持轻松集成到Xilinx Vivado设计流程和工具中。实验结果表明，验证时间显着加快，并且与通过我们的框架测得的板上延迟相比，Xilinx工具获得的协同仿真估计存在不准确之处。为此目的而开发的一组自动生成脚本支持轻松集成到Xilinx Vivado设计流程和工具中。实验结果表明，验证时间显着加快，并且与通过我们的框架测得的板上延迟相比，Xilinx工具获得的协同仿真估计存在不准确之处。