In this article, we analyzed the stability, power, performance, and area of 6T-SRAMs using a promising scaling booster, i.e., source/drain patterning (SDP) scheme for the 3-nm technology node based on 3-D TCAD simulation. SDP scheme allows to decrease the spacing between transistors by downsizing the source/drain epitaxy. Proposed 5-nm and 3-nm SDP-SRAM (SDP-SRAM ₅ and SDP-SRAM ₃ ) are compared with conventional 5-nm node SRAM (Conv-SRAM ₅ ), quantitatively. Unlike a Conv-SRAM ₅ , SDP-SRAMs have more design margins according to the two fin position parameters: fin location adjustment (FLA) and separation pitch adjustment (SPA). The optimized layout has the maximum FLA by significantly decreasing the back-end-of-line (BEOL) bitline and internal node capacitance. Read and write static noise margins were comparable (< 10 mV) between the SDP-SRAM and Conv-SRAM. The SDP-SRAM ₅ improved the read access time 18% compared to the Conv-SRAM ₅ in low-power (LP) applications, but the SDP-SRAM ₃ degraded it by 11% in high-performance (HP) applications because of the narrow M2 pitch. Both the SDP-SRAM ₅ and SDP-SRAM ₃ improved write access time about 10% compared to a Conv-SRAM ₅ in LP applications. The cell area of the SDP-SRAM ₃ decreased about 0.64 times compared to a Conv-SRAM ₅ without severe degradation of performance. The SDP scheme provides flexible layout designs enabling a high-density SRAM, promising for 3-nm node logic applications.

中文翻译：

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基于TCAD的3nm节点6T-SRAM的灵活鳍间距设计，采用了实用的源极/漏极构图方案

在本文中，我们使用了有前途的缩放助推器（即基于3-D TCAD仿真的3纳米技术节点的源/漏图案（SDP）方案）来分析6T-SRAM的稳定性，功率，性能和面积。SDP方案允许通过缩小源极/漏极外延来减小晶体管之间的间距。将拟议的5纳米和3纳米SDP-SRAM（SDP-SRAM ₅和SDP-SRAM ₃ ）与常规5纳米节点SRAM（Conv-SRAM ₅ ）进行定量比较。与Conv-SRAM _5不同 ，根据两个鳍位置参数，SDP-SRAM具有更多的设计余量：鳍位置调整（FLA）和间隔间距调整（SPA）。经过优化的布局可通过显着降低线路后端（BEOL）位线和内部节点电容来实现最大FLA。SDP-SRAM和Conv-SRAM之间的读写静态噪声容限相当（<10 mV）。与低功耗（LP）应用程序中的Conv-SRAM ₅相比，SDP-SRAM ₅的读取访问时间缩短了18％，但是在高性能（HP）应用中，SDP-SRAM ₃的读取访问时间 降低了11％。窄的M2音调。与Conv-SRAM ₅相比，SDP-SRAM ₅和SDP-SRAM _3的写入访问时间均缩短了约10％。 在LP应用程序中。与Conv-SRAM ₅相比，SDP-SRAM ₃的单元面积 减少了约0.64倍，而 性能却没有严重下降。SDP方案提供了灵活的布局设计，可实现高密度SRAM，有望用于3纳米节点逻辑应用。