Timing error is now getting increased attention due to the high rate of error-occurrence on semiconductors. Even slight external disturbance can threaten the timing margin between successive clocks since the latest semiconductor operates with high frequency and small supply voltage. To deal with a timing error, many techniques have been introduced. Nevertheless, existing methods that mitigate a timing error mostly have time-delaying mechanisms and too complex operation, resulting in a timing problem on clock-based systems and hardware overhead. In this article, we propose a novel timing-error-tolerant method that can correct a timing error instantly through a simple mechanism. By modifying a clock in a flip-flop, the proposed system can recover a timing error without the loss of time in the clock-based system. Furthermore, due to the compact mechanism, the proposed system has low hardware overhead in comparison with existing timing-error-tolerant systems that can recover the error instantly. To verify our method, the proposed circuit was extensively simulated by addressing PVT variations. Moreover, it was implemented in several benchmark designs, including a microprocessor.

中文翻译：

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通过控制时钟实现低功耗时序误差的电路

由于半导体上的错误发生率很高，因此时序错误现在引起了越来越多的关注。由于最新的半导体器件以高频率和低电源电压工作，因此即使是很小的外部干扰也可能威胁到连续时钟之间的时序裕量。为了处理定时误差，已经引入了许多技术。然而，减轻时序误差的现有方法大多具有延时机制和过于复杂的操作，从而导致基于时钟的系统和硬件开销方面的时序问题。在本文中，我们提出了一种新颖的定时误差容限方法，该方法可以通过一种简单的机制立即纠正定时误差。通过修改触发器中的时钟，所提出的系统可以恢复定时误差，而不会浪费基于时钟的系统中的时间。此外，由于具有紧凑的机制，与现有的可以即时恢复错误的定时容错系统相比，该系统的硬件开销较低。为了验证我们的方法，通过解决PVT变化对提议的电路进行了广泛的仿真。此外，它已通过多种基准设计实现，包括微处理器。