The integration of more components into modern integrated circuits (ICs) has led to very large RLC parasitic networks consisting of millions of nodes that have to be simulated in many times or frequencies to verify the proper operation of the chip. Model order reduction (MOR) techniques have been employed routinely to substitute the large-scale parasitic model with a model of lower order with a similar response at the input–output ports. However, established MOR techniques generally result in dense system matrices that render their simulation impractical. To this end, in this article, we propose a methodology for the sparsification of the dense circuit matrices resulting from MOR of general RLC circuits, which employs a sequence of algorithms based on the computation of the nearest diagonally dominant matrix and the sparsification of the corresponding graph. In addition, we describe a procedure for synthesizing the sparsified reduced-order model into an RLC circuit with only positive elements. Experimental results indicate that a high sparsity ratio of the reduced system matrices can be achieved with very small loss of accuracy.

中文翻译：

---

基于图的稀疏化与稠密矩阵的合成。 RLC 电路

将更多的组件集成到现代集成电路（IC）中已经导致了很大的发展。 RLC由数百万个节点组成的寄生网络，必须多次或多次对其进行仿真，以验证芯片的正常工作。惯常使用模型阶数减少（MOR）技术，以低阶模型代替大规模寄生模型，该模型在输入输出端口具有相似的响应。但是，已建立的MOR技术通常会导致密集的系统矩阵，从而使其仿真变得不切实际。为此，在本文中，我们提出了一种方法，用于稀疏化由一般MOR导致的密集电路矩阵RLC电路，它基于最近的对角线优势矩阵的计算和相应图形的稀疏化，采用了一系列算法。另外，我们描述了将稀疏的降阶模型合成为RLC仅包含正极元件的电路。实验结果表明，可以以极少的精度损失来实现高稀疏率的简化系统矩阵。