A 1024 $\times $ 896 test chip is presented in this article to explore a low-power readout circuit for a multi-bit quanta image sensor (QIS). Five well-known analog-to-digital converter (ADC) approaches [flash, pipeline, successive approximation register (SAR), cyclic, and single-slope (SS)] are studied, and two types of ADCs, namely, SAR ADCs and SS ADCs, are implemented in the sensor. The ADC power dissipations are compared under the condition of constant imaging throughput in counting photoelectrons. In QIS devices, one LSB corresponds to one photoelectron. Measurement results show that the power consumption of SAR ADC is better than that of the SS ADC and decreases by a factor of 17 when the resolution is changed from 1 b to 6 bits. By contrast, the power consumption of the SS ADCs decreases by a factor of 2.5. Thus, SAR ADCs seem more suitable for use in low-power multi-bit QIS.

中文翻译：

---

适用于多位Quanta图像传感器的低位深度ADC

一个1024 $ \次$ 本文介绍了896测试芯片，以探索用于多位量子图像传感器（QIS）的低功耗读出电路。研究了五种著名的模数转换器（ADC）方法[闪存，流水线，逐次逼近寄存器（SAR），循环和单斜率（SS）]，并且两种类型的ADC，即SAR ADC和SS ADC在传感器中实现。在对光电子计数时，在恒定成像吞吐量的条件下比较ADC功耗。在QIS器件中，一个LSB​​对应一个光电子。测量结果表明，SAR ADC的功耗优于SS ADC的功耗，并且当分辨率从1 b更改为6位时，功耗降低了17倍。相比之下，SS ADC的功耗降低了2.5倍。因此，