Purpose

High packaging density in the present VLSI era builds an acute power crisis, which limits the use of MOSFET device as a constituent block in CMOS technology. This leads researchers in looking for alternative devices, which can replace the MOSFET in CMOS VLSI logic design. In a quest for alternative devices, tunnel field effect transistor emerged as a potential alternative in recent times. The purpose of this study is to enhance the performances of the proposed device structure and make it compatible with circuit implementation. Finally, the performances of that circuit are compared with CMOS circuit and a comparative study is made to find the superiority of the proposed circuit with respect to conventional CMOS circuit.

Design/methodology/approach

Silicon–germanium heterostructure is currently one of the most promising architectures for semiconductor devices such as tunnel field effect transistor. Analytical modeling is computed and programmed with MATLAB software. Two-dimensional device simulation is performed by using Silvaco TCAD (ATLAS). The modeled results are validated through the ATLAS simulation data. Therefore, an inverter circuit is implemented with the proposed device. The circuit is simulated with the Tanner EDA tool to evaluate its performances.

Findings

The proposed optimized device geometry delivers exceptionally low OFF current (order of 10^−18 A/um), fairly high ON current (5x10^−5 A/um) and a steep subthreshold slope (20 mV/decade) followed by excellent ON–OFF current ratio (order of 10^13) compared to the similar kind of heterostructures. With a very low threshold voltage, even lesser than 0.1 V, the proposed device emerged as a good replacement of MOSFET in CMOS-like digital circuits. Hence, the device is implemented to construct a resistive inverter to study the circuit performances. The resistive inverter circuit is compared with a resistive CMOS inverter circuit. Both the circuit performances are analyzed and compared in terms of power dissipation, propagation delay and power-delay product. The outcomes of the experiments prove that the performance matrices of heterojunction Tunnel FET (HTFET)-based inverter are way ahead of that of CMOS-based inverter.

Originality/value

Germanium–silicon HTFET with stack gate oxide is analytically modeled and optimized in terms of performance matrices. The device performances are appreciable in comparison with the device structures published in contemporary literature. CMOS-like resistive inverter circuit, implemented with this proposed device, performs well and outruns the circuit performances of the conventional CMOS circuit at 45-nm technological node.

中文翻译：

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基于解析模型的Ge-Si异质结TFET的电路性能分析

目的

在当前的VLSI时代，高封装密度造成了严重的电源危机，这限制了MOSFET器件作为CMOS技术的组成部分的使用。这促使研究人员寻找替代器件，这些器件可以代替CMOS VLSI逻辑设计中的MOSFET。在寻求替代器件的过程中，隧道场效应晶体管近来已成为一种潜在的替代方案。这项研究的目的是增强所提出的器件结构的性能，并使其与电路实现兼容。最后，将该电路的性能与CMOS电路进行了比较，并进行了比较研究，以发现该电路相对于常规CMOS电路的优越性。

设计/方法/方法

硅锗异质结构目前是半导体器件（例如隧道场效应晶体管）最有前途的体系结构之一。使用MATLAB软件对分析模型进行计算和编程。使用Silvaco TCAD（ATLAS）进行二维设备仿真。通过ATLAS仿真数据验证了建模结果。因此，利用所提出的装置实现了逆变器电路。使用Tanner EDA工具对电路进行仿真，以评估其性能。

发现

拟议的优化器件几何结构可提供极低的截止电流（10 ^ −18 A / um量级），相当高的导通电流（5x10 ^ −5 A / um）和陡峭的亚阈值斜率（20 mV /十倍），随后具有出色的导通能力–OFF电流比（10 ^ 13的量级），与同类异质结构相比。所提出的器件具有非常低的阈值电压，甚至低于0.1 V，是CMOS类数字电路中MOSFET的良好替代品。因此，该装置被实现为构造电阻式逆变器以研究电路性能。将电阻反相器电路与电阻CMOS反相器电路进行比较。分析并比较了两种电路的性能，包括功耗，传播延迟和功率延迟乘积。

创意/价值

对具有堆叠栅氧化层的锗硅HTFET进行了分析建模，并根据性能矩阵进行了优化。与当代文献中公开的设备结构相比，该设备的性能是可观的。用此提出的器件实现的类CMOS电阻反相器电路在45 nm工艺节点上表现良好，并且超越了常规CMOS电路的电路性能。