Hardware performance counters (HPCs) that measure low-level architectural and microarchitectural events provide dynamic contextual information about the state of the system. However, HPC measurements are error-prone due to non determinism (e.g., undercounting due to event multiplexing, or OS interrupt-handling behaviors). In this paper, we present BayesPerf, a system for quantifying uncertainty in HPC measurements by using a domain-driven Bayesian model that captures microarchitectural relationships between HPCs to jointly infer their values as probability distributions. We provide the design and implementation of an accelerator that allows for low-latency and low-power inference of the BayesPerf model for x86 and ppc64 CPUs. BayesPerf reduces the average error in HPC measurements from 40.1% to 7.6% when events are being multiplexed. The value of BayesPerf in real-time decision-making is illustrated with a simple example of scheduling of PCIe transfers.

中文翻译：

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BayesPerf：使用贝叶斯统计信息最小化性能监视错误

度量低级架构和微架构事件的硬件性能计数器（HPC）提供有关系统状态的动态上下文信息。但是，由于不确定性，HPC测量容易出错（例如，由于事件多路复用或OS中断处理行为而导致计数不足）。在本文中，我们介绍了BayesPerf，这是一种通过使用域驱动的贝叶斯模型来量化HPC测量不确定性的系统，该模型捕获HPC之间的微体系结构关系，以共同推断其值作为概率分布。我们提供了加速器的设计和实现，该加速器允许针对x86和ppc64 CPU的BayesPerf模型进行低延迟和低功耗推断。当事件被多路复用时，BayesPerf将HPC测量的平均误差从40.1％降低到7.6％。