In this article, a power-efficient hybrid voltage up level shifter (LS) is designed. By using a combination of a current mirror (CM) and a cross-coupled pMOS pair in a pull-up circuitry, the dynamic power is reduced significantly even at boosted switching speed. The designed LS circuit, which occupies a small silicon area, consists of 10 transistors and is mainly suitable for ultra-low-power applications, such as wireless sensor nodes and biomedical appliances. Moreover, it can convert extreme low-level input voltages to the high supply voltage levels. The results obtained from post-layout simulations in a standard 180-nm CMOS process illustrate that the designed LS circuit has total power consumption, static power dissipation, and propagation delay of 33.93 nW, 253 pW, and 9.09 ns, respectively, at 1 MHz with a minimum supply voltage (V_DDL) of 0.4 V and nominal supply voltage (V_DDH) of 1.8 V. Also, the designed LS can convert an input voltage of 0.12–1.8 V at 10 kHz.

中文翻译：

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具有低功率延迟产品的高能效升压电平转换器

在本文中，设计了一种高能效混合升压电平转换器 (LS)。通过在上拉电路中结合使用电流镜 (CM) 和交叉耦合的 pMOS 对，即使在提高开关速度的情况下，动态功耗也能显着降低。所设计的 LS 电路占用的硅面积很小，由 10 个晶体管组成，主要适用于超低功耗应用，如无线传感器节点和生物医学设备。此外，它还可以将极低电平的输入电压转换为高电源电压电平。从标准 180-nm CMOS 工艺中的布局后仿真获得的结果表明，设计的 LS 电路在 1 MHz 下的总功耗、静态功耗和传播延迟分别为 33.93 nW、253 pW 和 9.09 ns具有最小电源电压（V _DDL ) 为 0.4 V，标称电源电压 ( V _DDH ) 为 1.8 V。此外，设计的 LS 可以在 10 kHz 时转换 0.12–1.8 V 的输入电压。