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An electrothermal compact model of SiC MOSFETs for analyzing avalanche failure mechanisms
Japanese Journal of Applied Physics ( IF 1.5 ) Pub Date : 2021-02-17 , DOI: 10.35848/1347-4065/abdc5c
Kyohei Shimozato , Yohei Nakamura , Song Bian , Takashi Sato

Avalanche failure that occurs in circuits with inductive loads is an important issue facing silicon carbide (SiC) metal–oxide–semiconductor field-effect transistors (MOSFETs). Two mechanisms have been suggested for this failure: the activation of a parasitic bipolar junction transistor (BJT), and the intrinsic operation of SiC at extremely high temperatures. In this study, we propose a SPICE-based electrothermal simulation model of SiC MOSFETs to simulate avalanche behavior. The proposed compact MOSFET model includes a parasitic BJT, a body diode, and an intrinsic resistance. The intrinsic resistor represents the decreasing resistance of SiC due to its intrinsic operation in extremely high temperatures. The simulation results of our model accurately reproduce the measurement results of an unclamped inductive switching (UIS) test. According to the simulation results, the main cause of MOSFET failure in the UIS test is that SiC enters intrinsic operation because of the rapid increase of junction temperature over 1200 K.



中文翻译:

用于分析雪崩失效机制的 SiC MOSFET 电热紧凑模型

在具有感性负载的电路中发生的雪崩故障是碳化硅 (SiC) 金属氧化物半导体场效应晶体管 (MOSFET) 面临的一个重要问题。针对这种故障提出了两种机制:寄生双极结型晶体管 (BJT) 的激活,以及 SiC 在极高温度下的固有操作。在这项研究中,我们提出了一种基于 SPICE 的 SiC MOSFET 电热仿真模型来模拟雪崩行为。所提出的紧凑型 MOSFET 模型包括寄生 BJT、体二极管和本征电阻。本征电阻器代表 SiC 由于其在极高温度下的固有操作而降低的电阻。我们模型的仿真结果准确地再现了非钳位感应开关 (UIS) 测试的测量结果。

更新日期:2021-02-17
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