Purpose

The purpose of this paper is to implement a highly linear 180 nm complementary metal oxide semiconductor (CMOS) power amplifier (PA) to meet the stringent linearity requirement of an long term evolution (LTE) signal with minimum trade-off to power added efficiency (PAE).

Design/methodology/approach

The CMOS PA is designed in a cascaded dual-stage configuration comprises a driver amplifier and a main PA. The gate voltage (VGS) of the driver amplifier is tuned to optimize its positive third-order transconductance (g_m3) to be canceled with the main PA’s fixed negative g_m3. The g_m3 cancellation between these stages mitigates the third-order intermodulation product (IMD3) that contributes to enhanced linearity.

Findings

For driver’s VGS of 0.82 V with continuous wave signal, the proposed PA achieved a power gain of 14.5 dB with a peak PAE of 31.8% and a saturated output power of 23.3 dBm at 2.45 GHz. A maximum third-order output intercept point of 34 dBm is achieved at 20.2 dBm output power with a corresponding IMD3 of −33.4 dBc. When tested with a 20 MHz LTE signal, the PA delivers 19 dBm maximum linear output power for an adjacent channel leakage ratio specification of −30 dBc.

Originality/value

In this study, a novel cascaded g_m3 cancellation technique has been implemented to achieve a maximum linear output power under modulated signals.

中文翻译：

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具有三阶 gm 消除线性化技术的 23.3 dBm CMOS 功率放大器，可实现 34 dBm 的 OIP3

目的

本文的目的是实现一个高度线性的 180 nm 互补金属氧化物半导体 (CMOS) 功率放大器 (PA)，以满足长期演进 (LTE) 信号的严格线性要求，同时对功率附加效率的权衡最小( PAE)。

设计/方法/方法

CMOS PA 采用级联双级配置设计，包括驱动放大器和主 PA。调整驱动放大器的栅极电压 (VGS) 以优化其正三阶跨导 (g _m3 ) 以与主 PA 的固定负 g _m3抵消。这些级之间的 g _m3抵消减轻了有助于增强线性度的三阶互调产物 (IMD3)。

发现

对于 0.82 V 的驱动器 VGS 和连续波信号，所提出的 PA 实现了 14.5 dB 的功率增益，峰值 PAE 为 31.8%，在 2.45 GHz 时的饱和输出功率为 23.3 dBm。在 20.2 dBm 的输出功率下实现了 34 dBm 的最大三阶输出截点，相应的 IMD3 为 −33.4 dBc。当使用 20 MHz LTE 信号进行测试时，PA 提供 19 dBm 的最大线性输出功率，相邻信道泄漏比规格为 -30 dBc。

原创性/价值

在这项研究中，已经实施了一种新颖的级联 g _{m3消除技术，以在调制信号下实现最大线性输出功率。}