Latency-insensitive design mitigates increasing interconnect delay and enables productive component reuse in complex digital systems. This design style has been adopted in high-level design flows because untimed functional blocks connected through latency-insensitive interfaces provide a natural communication abstraction. However, latency-insensitive design with high-level languages also introduces a unique set of verification challenges that jeopardize functional correctness. In particular, bugs due to invalid consumption of inputs and deadlocks can be difficult to detect and debug with dynamic simulation methods. To tackle these two classes of bugs, we propose formal model checking methods to guarantee that a high-level latency-insensitive design is unaffected by invalid input data and is free of deadlock. We develop a well-structured verification wrapper for each property to automatically construct the corresponding formal model for checking. Our experiments demonstrate that the formal checks are effective in realistic bug scenarios from high-level designs.

中文翻译：

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使用正式模型检查来验证高级延迟不敏感的设计

延迟不敏感的设计减轻了互连延迟的增加，并在复杂的数字系统中实现了生产组件的重用。这种设计风格已在高层设计流程中采用，因为通过不依赖等待时间的接口连接的未计时功能块提供了自然的通信抽象。但是，采用高级语言的对延迟不敏感的设计也带来了一系列独特的验证挑战，这些挑战会危害功能的正确性。特别是，由于使用无效输入和死锁而导致的错误可能很难通过动态仿真方法进行检测和调试。为了解决这两类错误，我们提出了正式的模型检查方法，以确保高级时延不敏感的设计不受无效输入数据的影响，并且没有死锁。我们为每个属性开发了结构良好的验证包装程序，以自动构造相应的形式化模型进行检查。我们的实验表明，正式检查在高级设计的实际错误场景中是有效的。