Abstract

It is established that the electrophysical characteristics of MOS transistors largely depend on the quality of a gate dielectric. The presence of an extra built-in charge in the dielectric and fast surface states at the SiO₂/Si interface leads to both an increased threshold voltage and decreased saturation current and voltage, decreased slopes of the characteristics of the MOS transistor in the linear and saturation regions, and a decreased structure conductance in the linear region. The gate leakage currents also increase. It is shown that the view and shape of the capacity–voltage characteristics are determined by the value of an extra positive charge in the bulk of the dielectric and the density of fast surface states at the Si/SiO₂ interface. These values are correlated to the profile of the distribution of the surface concentration of the process-related impurities adsorbed at the wafer surface during the manufacturing of the device, which allows us to judge the quality of the materials used, adherence to the production conditions, and, if necessary, correct them opportunely as required.

中文翻译：

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与工艺有关的杂质对MOS晶体管电物理参数的影响

摘要

已经确定，MOS晶体管的电物理特性在很大程度上取决于栅极电介质的质量。介电常数和SiO ₂ / Si界面处的快速表面状态中存在额外的内置电荷会导致阈值电压增加以及饱和电流和电压减小，线性和垂直状态下MOS晶体管的特性斜率减小。饱和区域，线性区域的结构电导降低。栅极泄漏电流也增加。结果表明，电容-电压特性的视图和形状取决于电介质主体中额外的正电荷的值以及Si / SiO ₂处快速表面态的密度界面。这些值与设备制造过程中吸附在晶片表面的过程相关杂质的表面浓度分布的分布相关，这使我们能够判断所用材料的质量，对生产条件的遵守程度，并在必要时根据需要进行更正。