Static random access memory (SRAM) bit cell is a prominent element for portable devices. The popularity of sleek designs and demand for longer battery life has driven memory cell into nanometer domain. This has also bolstered the need for low‐voltage devices. But reduction in operational voltage for cell is limited by process variation. In this work, a single bit line seven‐transistor (7T) SRAM bit cell is reported. The cell is designed for 32‐nm technology node and is functional at 300 mV. The reported cell maintains a 90‐mV hold and read static noise margins (SNMs), while the write margin is 190 mV. The pulse width needed to successfully write into the cell is 30 ns. The performance of proposed 7T cell is compared against different 6T, 7T, 8T, and 10T SRAM bit cells. The hold and read SNMs for proposed 7T are found to be 58.8%, better than single‐ended 6T cell, while the write ability is improved by 71.4%. The leakage current is observed to have decreased by a factor of 14 for Q = 0 (Q being the data storage node) and by factor of 28 for Q = 1, compared to 6T cell. Also, the area footprint of the proposed 7T SRAM cell is 0.442 μm².

中文翻译：

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单个位线访问的高性能超低压工作7T静态随机存取存储单元，具有提高的读取稳定性

静态随机存取存储器（SRAM）位单元是便携式设备的重要组成部分。时尚设计的普及以及对更长电池寿命的需求已将存储单元推向纳米领域。这也增加了对低压设备的需求。但是电池的工作电压的降低受到工艺变化的限制。在这项工作中，报告了单个位线七晶体管（7T）SRAM位单元。该单元专为32纳米技术节点而设计，可在300 mV的电压下正常工作。报告的单元保持90 mV的保持，并读取静态噪声容限（SNM），而写容限为190 mV。成功写入单元所需的脉冲宽度为30 ns。将建议的7T单元的性能与不同的6T，7T，8T和10T SRAM位单元进行比较。建议的7T的保留和读取SNM为58.8％，优于单端6T单元，而写入能力提高了71.4％。观察到泄漏电流降低了14倍，Q = 0（Q是数据存储节点），与6T单元相比，Q = 1的因数是28 。此外，所提出的7T SRAM单元的面积足迹是0.442微米²。