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TrackLace: Data Management for Interlaced Magnetic Recording
IEEE Transactions on Computers ( IF 3.7 ) Pub Date : 2021-03-01 , DOI: 10.1109/tc.2020.2988257
Fenggang Wu 1 , Bingzhe Li 1 , Baoquan Zhang 1 , Zhichao Cao 1 , Jim Diehl 1 , Hao Wen 1 , David H.C. Du 1
Affiliation  

Interlaced Magnetic Recording (IMR) is a promising technology which achieves higher data density and lower write amplification (WA) than Shingled Magnetic Recording (SMR). In IMR, top tracks and bottom tracks are interlaced so each bottom track is partially overlapped with two adjacent top tracks. Top tracks can be updated without any WA, but bottom track updates require reading and rewriting of affected valid data on the two neighboring top tracks. There are few published studies discussing WA in IMR drives. We propose TrackLace to reduce WA for IMR. TrackLace consists of three techniques: Z-Alloc allocates user data to the tracks in alternating directions and spreads unallocated tracks among allocated tracks; Top-Buffer opportunistically utilizes unallocated top tracks to buffer bottom track updates; and Block-Swap progressively swaps bottom track hot data with top track cold data during high space utilization. To further optimize TrackLace performance, we propose a virtual frame design that can keep the relocated block (due to Top-Buffer or Block-Swap) close to its original location and an adaptive buffering mechanism that can avoid unnecessary redirections depending on the write locality. Evaluations show that TrackLace can reduce WA by 45% and lower average latency by 31% compared with baseline schemes.

中文翻译:

TrackLace:隔行磁记录的数据管理

隔行磁记录 (IMR) 是一种很有前途的技术,与叠瓦式磁​​记录 (SMR) 相比,它可实现更高的数据密度和更低的写入放大 (WA)。在 IMR 中,顶部轨道和底部轨道是交错的,因此每个底部轨道与两个相邻的顶部轨道部分重叠。顶部轨道可以在没有任何 WA 的情况下更新,但底部轨道更新需要读取和重写两个相邻顶部轨道上受影响的有效数据。很少有已发表的研究讨论 IMR 驱动器中的 WA。我们建议使用 TrackLace 来减少 IMR 的 WA。TrackLace 由三种技术组成: Z-Alloc 将用户数据以交替方向分配给轨道,并在已分配轨道之间传播未分配的轨道;Top-Buffer 机会性地利用未分配的顶部轨道来缓冲底部轨道更新;在高空间利用率期间,Block-Swap 逐渐将底部轨道热数据与顶部轨道冷数据交换。为了进一步优化 TrackLace 性能,我们提出了一种虚拟帧设计,可以将重定位的块(由于顶部缓冲区或块交换)保持在其原始位置附近,以及一种自适应缓冲机制,可以根据写入位置避免不必要的重定向。评估表明,与基线方案相比,TrackLace 可以将 WA 降低 45%,并将平均延迟降低 31%。我们提出了一种虚拟帧设计,可以将重定位的块(由于顶部缓冲区或块交换)保持在其原始位置附近,以及一种自适应缓冲机制,可以根据写入位置避免不必要的重定向。评估表明,与基线方案相比,TrackLace 可以将 WA 降低 45%,并将平均延迟降低 31%。我们提出了一种虚拟帧设计,可以将重定位的块(由于顶部缓冲区或块交换)保持在其原始位置附近,以及一种自适应缓冲机制,可以根据写入位置避免不必要的重定向。评估表明,与基线方案相比,TrackLace 可以将 WA 降低 45%,并将平均延迟降低 31%。
更新日期:2021-03-01
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