In this paper, the ESD discharge capability of GGNMOS (gate grounded NMOS) device in the radiation-hardened 0.18 μm bulk silicon CMOS process (Rad-Hard by Process: RHBP) is optimized by layout and ion implantation design. The effects of gate length, DCGS and ESD ion implantation of GGNMOS on discharge current density and lattice temperature are studied by TCAD and device simulation. The size of DCGS, multi finger number and single finger width of ESD verification structures are designed, and the discharge capacity and efficiency of GGNMOS devices in ESD are characterized by TLP test technology. Finally, the optimized GGNMOS is verified on the DSP circuit, and its ESD performance is over 3500 V in HBM mode.

本文通过布局和离子注入设计优化了GGNMOS（栅极接地NMOS）器件在抗辐射0.18μm体硅CMOS工艺（Rad-Hard by Process：RHBP）中的ESD放电能力。通过TCAD和器件仿真研究了GGNMOS栅极长度、DCGS和ESD离子注入对放电电流密度和晶格温度的影响。设计了ESD验证结构的DCGS尺寸、多指数量和单指宽度，并通过TLP测试技术表征了GGNMOS器件在ESD中的放电容量和效率。最后在DSP电路上验证优化后的GGNMOS，其ESD性能在HBM模式下超过3500V。