This article presents a low-complexity digital low-dropout regulator (DLDO) design featuring a novel voltage regulation and transient enhancement scheme, and a charge-redistribution-based ripple suppression (CRRS) technique that smooths output by redistribution of excessive energy via a small capacitor. Also proposed is a fast-turnaround general DLDO design approach comprising a hybrid discrete-continuous DLDO model and techniques for modeling nonlinear performance enhancement techniques, with which a DLDO's performances for given specifications can be evaluated in the early design stage to shorten the development time. A DLDO test chip fabricated using 110 nm CMOS technology shows a fast settling time of 67 and 250 ns for light-to-heavy (i.e., 2.5 and 50 mA) and heavy-to-light transient, and an output voltage ripple as low as 3 mV with proposed CRRS. The core occupies only 0.022 mm ² , thanks to the resource-sharing architecture of a proposed digital controller and hardware simplicity. With an input voltage of 1 V and output voltage of 0.85 V, proposed design achieves a peak current efficiency of 99.6% with a 100 MHz operating clock frequency.

中文翻译：

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具有3 mV波纹的快速瞬态数字低压降稳压器的快速转换设计和建模技术

本文介绍了一种低复杂度的数字低压降稳压器（DLDO）设计，该设计具有新颖的电压调节和瞬态增强方案，以及一种基于电荷分配的波纹抑制（CRRS）技术，该技术可通过少量重新分配过多的能量来平滑输出。电容器。还提出了一种快速周转的通用DLDO设计方法，该方法包括混合离散-连续DLDO模型和用于对非线性性能增强技术进行建模的技术，利用该技术可以在设计的早期阶段评估给定规格的DLDO性能，以缩短开发时间。使用110 nm CMOS技术制造的DLDO测试芯片对于轻到重（即2.5和50 mA）和重到轻的瞬态，显示出67 ns和250 ns的快速建立时间，建议采用CRRS的输出电压纹波低至3 mV。核心仅占0.022毫米 ^{如图2所示} ，这要归功于所提出的数字控制器的资源共享架构以及硬件的简单性。提出的设计在输入电压为1 V，输出电压为0.85 V的情况下，以100 MHz的工作时钟频率实现了99.6％的峰值电流效率。