This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate’s capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this brief, all three architectures are revisited.

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线性低压差稳压器的最新进展

本文简要介绍了线性低压差稳压器的最新设计趋势。讨论了模拟LDO（ALDO）的设计问题和优势。当提供大电流值时，高性能操作和对电源噪声的高抑制能力是ALDO的主要优势，但从待机状态过渡到满载状态时的瞬态响应则是一个主要问题。主要限制是传输晶体管的大栅极电容器的缓慢充电/放电。在设计没有大型负载电容器的全芯片ALDO时，这个问题尤为关键。数字LDO（DLDO）采用数字控制器来驱动分段传输晶体管，在大多数情况下，它们在三极管区域内工作。DLDO的数字性质随该技术而扩展，但其对电源噪声的抑制作用有限。混合模式LDO充分利用了ALDO和DLDO的特性。瞬态由敏捷的DLDO管理，稳态操作主要由无时钟毛刺的ALDO处理。在本简介中，将重新讨论所有三种体系结构。