This brief presents the design and sizing of a femto-watt voltage reference based on the temperature compensation of N-type and P-type standard transistors. A short-channel dimension transistor working in triode region is added between the source and gate terminals of the traditional self-bias structure, which demonstrates efficient low-power and low-voltage operations. The circuit design was carried out in a 180 nm process. Post-layout simulation results verified the proper circuit operation and produced a reference voltage of 65.7 mV. With a minimum supply voltage of 120 mV, the circuit consumes 252 fW at room temperature, has mean and best temperature coefficients (TCs) of 89.81 ppm/°C and 10.61 ppm/°C, respectively, from −40 to 120°C, and presents a power supply rejection ratio (PSRR) of −61 dB.

中文翻译：

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120 mV电源，三极管调节的Femto-Watt CMOS电压参考设计

本简介介绍了基于N型和P型标准晶体管的温度补偿的飞瓦电压基准的设计和尺寸。在传统的自偏置结构的源极端子和栅极端子之间添加了一个在三极管区域工作的短沟道尺寸晶体管，该晶体管演示了有效的低功耗和低压操作。电路设计是在180 nm工艺中进行的。布局后的仿真结果验证了电路的正确运行，并产生了65.7 mV的参考电压。在最低电源电压为120 mV的情况下，该电路在室温下的功耗为252 fW，在-40至120°C范围内的平均和最佳温度系数（TC）分别为89.81 ppm /°C和10.61 ppm /°C，的电源抑制比（PSRR）为-61 dB。