The great demand of high‐performance fixed‐width two's‐complement modified Booth multipliers (FWBM) arises because of the wide applications of approximate computing. In this paper, a row‐based direct‐mapping (RDM) method for designing error estimators in FWBM is proposed. The proposed closed form is derived from probability summation of each entire row to avoid the long setup time of exhaustive simulations. Consequently, a simple and systematic procedure by the Karnaugh map can be utilized to design low‐error and hardware‐efficient compensation circuits for various widths of FWBMs. By checking the leading column of the truncation part, the extendable design principle can be easily applied to different lengths and different columns inspected. We use Synopsys Design Compiler and TSMC 90 nm standard cell library to synthesize the register transfer language (RTL) design of our proposed estimators. In addition, the RDM is synthesized using the Xilinx Vivado tool with Xilinx Kintex‐7 XC7K325T‐2FFG900C FPGA. Results of software simulation, hardware synthesis, and implementation experiment validate the high accuracy, hardware saving, and power efficiency of the proposed RDM estimators.

中文翻译：

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固定宽度修改的Booth乘法器中的简单且硬件有效的基于行的直接映射估计器

由于近似计算的广泛应用，对高性能固定宽度二进制补码修改的Booth乘法器（FWBM）提出了很高的要求。本文提出了一种基于行的直接映射（RDM）方法来设计FWBM中的误差估计器。所提出的封闭形式是从每整行的概率求和中得出的，以避免详尽的模拟过程设置时间长。因此，可以利用卡诺图的简单而系统的程序来设计用于各种宽度的FWBM的低误差和硬件效率的补偿电路。通过检查截断部分的前列，可扩展的设计原理可以轻松地应用于不同长度和检查过的不同列。我们使用Synopsys设计编译器和TSMC 90 nm标准单元库来合成我们提出的估算器的寄存器传输语言（RTL）设计。此外，RDM是使用Xilinx Vivado工具和Xilinx Kintex-7 XC7K325T-2FFG900C FPGA进行合成的。软件仿真，硬件综合和实现实验的结果验证了所提出的RDM估算器的高精度，硬件节省和电源效率。