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A Programmable Checker for Automated 2.5-D/3-D IC ESD Verification
IEEE Transactions on Components, Packaging and Manufacturing Technology ( IF 2.2 ) Pub Date : 2020-11-20 , DOI: 10.1109/tcpmt.2020.3039608
Dina Medhat , Mohamed Dessouky , Diaaeldin Khalil

Electrostatic discharge (ESD) robustness is an extremely important aspect in integrated circuits (ICs) and is well established for regular 2-D ICs. However, 2.5-D and 3-D integration present new challenges in both design and verification. While several studies have focused on design methodologies to achieve effective ESD protection in 2.5-D and 3-D ICs, there is a lack of research into automated ESD verification solutions for these technologies. Therefore, this article focuses on automated ESD verification in 2.5-D and 3-D ICs. We explain the verification challenges introduced by these integration technologies and propose an automated ESD verification methodology for 2.5-D and 3-D ICs. We implement this methodology in a programmable checker to automate the verification for complete 2.5-D and 3-D IC designs. The checker differentiates between external and internal inputs/outputs from the assembly level without the use of layout markers on the die level. It checks for correct, incorrect, and missing ESD protection circuitries for each category of inputs/outputs. It checks total parasitic resistance and performs current density analysis for the relevant interconnect routes through the entire 3-D IC design layout to ensure these routes can sustain the ESD event. We apply our proposed checker to a test case that includes 2.5-D and 3-D-specific ESD challenges and demonstrate its effectiveness.

中文翻译:

用于自动2.5-D / 3-D IC ESD验证的可编程检查器

静电放电(ESD)的鲁棒性是集成电路(IC)中极为重要的一个方面,并且对于常规的2D IC已有很好的确立。但是,2.5维和3维集成在设计和验证方面都提出了新的挑战。尽管有几项研究专注于在2.5D和3D IC中实现有效ESD保护的设计方法,但仍缺乏针对这些技术的自动ESD验证解决方案的研究。因此,本文重点介绍2.5D和3D IC中的自动ESD验证。我们解释了这些集成技术带来的验证挑战,并提出了针对2.5D和3D IC的自动ESD验证方法。我们在可编程检查器中实施此方法,以自动完成完整的2.5D和3D IC设计验证。该检查器可从装配级别区分外部和内部输入/输出,而无需在管芯级别使用布局标记。它检查每种输入/输出类别的ESD保护电路是否正确,不正确以及是否丢失。它检查整个寄生电阻,并针对整个3D IC设计布局中的相关互连路径执行电流密度分析,以确保这些路径可以承受ESD事件。我们将建议的检查器应用于包含2.5D和3D特定ESD挑战的测试案例,并证明其有效性。它检查整个寄生电阻,并针对整个3D IC设计布局中的相关互连路径执行电流密度分析,以确保这些路径可以承受ESD事件。我们将建议的检查器应用于包含2.5D和3D特定ESD挑战的测试案例,并证明其有效性。它检查整个寄生电阻,并针对整个3D IC设计布局中的相关互连路径执行电流密度分析,以确保这些路径可以承受ESD事件。我们将建议的检查器应用于包含2.5D和3D特定ESD挑战的测试案例,并证明其有效性。
更新日期:2021-01-26
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