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Hardware-Aware Design for Edge Intelligence
IEEE Open Journal of Circuits and Systems Pub Date : 2020-12-30 , DOI: 10.1109/ojcas.2020.3047418
Warren J. Gross , Brett H. Meyer , Arash Ardakani

With the rapid growth of the number of devices connected to the Internet, there is a trend to move intelligent processing of the generated data with deep neural networks (DNNs) from cloud servers to the network edge. Performing inference and training of DNNs in edge hardware is motivated by latency constraints, security and privacy concerns, and restricted network bandwidth. However, implementation of DNNs is challenging in resource-constrained edge devices. This article surveys recent advances in the efficient processing of DNNs, highlighting present research trends and future challenges. Specifically, we start by reviewing optimization methods for hardware-aware deployment of DNNs. We then present some case studies of promising new directions towards low-complexity on-chip training. Finally, we discuss future challenges and their potential solutions for efficient deployment of DNNs at the edge.

中文翻译:

边缘智能的硬件感知设计

随着连接到Internet的设备数量的快速增长,趋势是将通过深度神经网络(DNN)对生成的数据进行智能处理从云服务器转移到网络边缘。延迟限制,安全性和隐私问题以及受限的网络带宽推动了在边缘硬件中执行DNN的推理和训练。但是,在资源受限的边缘设备中,DNN的实现具有挑战性。本文调查了DNN高效处理的最新进展,重点介绍了当前的研究趋势和未来的挑战。具体来说,我们首先回顾DNN的硬件感知部署的优化方法。然后,我们介绍一些案例研究,这些案例有望为低复杂度的芯片培训提供新的方向。最后,
更新日期:2021-01-22
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