A 4-bit Carry Look-Ahead (CLA) architecture for carry-generation process is proposed. CLA architecture proposed in this work uses complex CLA circuits for carry-generation rather than using carry-generate and carry-propagate functions which are used in the conventional process of 4-bit CLA architecture. Performance of the proposed CLA architecture is validated by performing simulation utilizing Cadence tools in standard 45 ​nm CMOS process. In order to prove effectiveness, performance of the proposed 4-bit CLA design is compared with existing 4-bit CLA designs. Moreover, as a possible application of the proposed design and to inspect performance in wide word length adder structure, the 4-bit CLA architectures (proposed and existing) are extended to 16-bits using Carry-Select Adder (CSA) architecture. Both as 4-bit cell and extended 16-bit structure, the proposed 4-bit CLA shows remarkable improvement in speed while maintaining quite acceptable level of power consumption. As a result, the proposed 4-bit CLA can be utilized as a highly suitable substitution of the existing 4-bit CLA architectures in high-speed microprocessor design.

提出了一种用于进位生成过程的4位进位超前（CLA）架构。在这项工作中提出的CLA体系结构使用复杂的CLA电路进行进位生成，而不是使用传统的4位CLA体系结构处理中使用的进位生成和进位传播功能。通过在标准45纳米CMOS工艺中使用Cadence工具进行仿真来验证所提出的CLA体系结构的性能。为了证明有效性，将建议的4位CLA设计的性能与现有的4位CLA设计进行了比较。此外，作为拟议设计的可能应用并检查宽字长加法器结构中的性能，使用进位选择加法器（CSA）将4位CLA体系结构（建议的和现有的）扩展为16位。作为4位单元和扩展的16位结构，建议的4位CLA在保持相当可接受的功耗水平的同时，还显示出速度的显着提高。结果，提出的4位CLA可以用作高速微处理器设计中现有4位CLA体系结构的高度合适的替代品。