This paper presents a power-efficient successive-approximation register (SAR) analog-to-digital converter (ADC) with fast response reference buffer (RV-buffer). Several techniques are applied in the system design to improve the performance of the SAR ADC. A novel timing-redistribution SAR logic is proposed to balance the difference between required settling time for the most significant bit and the least significant bits (LSBs) in the digital-to-analog capacitor array, which reduces the incomplete settling error and releases the requirements on the RV-buffer to achieve lower power dissipation. The SAR ADC is fabricated in 40-nm CMOS technology occupying 0.13 mm\(^{2}\) area. At 1.1 V supply voltage and 80 MHz sampling frequency, the ADC achieves 50.7 dB SNDR, 69.5 dBc SFDR with a 1 MHz input at −8 dBFS. The total power consumption of the ADC is 2.99 mW, including the reference buffer power consumption of 2 mW. The Schreier FoM is 164.1 dB.

本文提出了一种具有快速响应参考缓冲器（RV缓冲器）的高能效逐次逼近寄存器（SAR）模数转换器（ADC）。在系统设计中应用了多种技术来改善SAR ADC的性能。提出了一种新颖的时序分配SAR逻辑，以平衡数模电容器阵列中最高有效位和最低有效位（LSB）所需的建立时间之间的差异，从而减少了不完整的建立误差并释放了要求在RV缓冲器上实现较低的功耗。SAR ADC采用40纳米CMOS技术制造，占地0.13毫米\（^ {2} \）区。在1.1 V电源电压和80 MHz采样频率下，ADC达到50.7 dB的SNDR，69.5 dBc的SFDR，并且在−8 dBFS的条件下具有1 MHz输入。ADC的总功耗为2.99 mW，其中包括2 mW的基准缓冲器功耗。Schreier FoM为164.1 dB。