This paper presents a single-coarse dual-fine architecture that improves energy-efficiency of pipelined-SAR analog-to-digital converters (ADCs). A coarse and fast sub-ADC is used to quantize the most significant bits (MSBs), which are encoded with a proposed residue transformation method to control the residue generation of the first stages in two fine channels. The residue voltages generate on the capacitive digital-to-analog converters (C-DACs) of split fine channels directly without successive approximation processes. Therefore, the conversion rate is increased and the power is reduced. A shuffle mechanism is introduced into split-ADC based digital background calibration to avoid the divergence of the conventional algorithm in the proposed architecture. A high-energy-efficiency dynamic amplifier is also introduced as the residue amplifier. A 14-bit 60-MS/s ADC is prototyped in a 28-nm CMOS process. The digital calibration engine operates under 0.9-V supply, other parts of the ADC core operate under 1.05-V supply. The ADC core consumes 4.26 mW. Measurement results show that the calibration improved the signal-to-noise and distortion ratio (SNDR) and spur-free dynamic range (SFDR) dramatically, the calibrated ADC achieves SNDR and SFDR of 66.9 dB and of 91.0 dB respectively, translating to a Schreier FoM of 165.4 dB and a Walden FoM of 39.3 fJ/conversion-step.

中文翻译：

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91.0dB SFDR 单粗双精细流水线 SAR ADC，在 28-nm CMOS 中具有基于分离的背景校准

本文介绍了一种单粗双精细架构，可提高流水线 SAR 模数转换器 (ADC) 的能效。粗略和快速子 ADC 用于量化最高有效位 (MSB)，最高有效位 (MSB) 使用建议的残差变换方法进行编码，以控制两个细通道中第一级的残差生成。残余电压直接在分离精细通道的电容数模转换器 (C-DAC) 上生成，无需逐次逼近过程。因此，转换率提高，功率降低。在基于拆分 ADC 的数字背景校准中引入了 shuffle 机制，以避免所提出的架构中传统算法的发散。还引入了一个高能效动态放大器作为残余放大器。14 位 60-MS/s ADC 原型采用 28-nm CMOS 工艺。数字校准引擎在 0.9V 电源下运行，ADC 内核的其他部分在 1.05V 电源下运行。ADC 内核消耗 4.26 mW。测量结果表明，校准显着提高了信噪比和无杂散动态范围 (SFDR)，校准后的 ADC 分别实现了 66.9 dB 和 91.0 dB 的 SNDR 和 SFDR，转换为 Schreier FoM 为 165.4 dB，Walden FoM 为 39.3 fJ/转换步长。