Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enabling flexible bus connections in a grid of processing elements containing switches. RM algorithms have theoretical results proving that switching+signal−broadcasting can speed up computations significantly. However, the RM assumes that the latency of broadcasting a signal through n switches (bus length) is 1. This is an unrealistic assumption preventing physical realizations of the RM. We propose the restricted-RM (RRM) wherein the bus lengths are restricted to k=n1d, d=2,3,…. We show that counting the number of 1-bits in an input of n bits can be done in 2⋅d steps for d=2,3,… by an n×n RRM. An almost matching lower bound is presented, using a technique which adds to the few existing lower-bound techniques in this area. Finally, the algorithm was directly coded over an FPGA, outperforming an optimal tree of adders. This work presents an alternative way of counting, which is fundamental for summing, beating regular Boolean circuits for large numbers, where summing a vast amount of numbers is the basis of any accelerator in embedded systems such as neural-nets and streaming.^a

中文翻译：

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可重构网格计数算法的FPGA实现

传输晶体管逻辑 (PTL) 是一种电路设计技术，其中晶体管用作开关。可重构网格 (RM) 是一种利用 PTL 信号切换功能的模型，通过在包含开关的处理元件网格中实现灵活的总线连接。RM算法有理论结果证明交换+信号-广播可以显着加快计算速度。然而，RM 假设通过n开关（总线长度）为 1。这是一个不切实际的假设，阻碍了 RM 的物理实现。我们提出了受限制的 RM (RRM)，其中总线长度限制为ķ=n1d,d=2,3,…. 我们证明了计算输入中 1 位的数量n位可以在2⋅d步骤d=2,3,…由一个n×nRRM。提出了一个几乎匹配的下限，使用一种技术，该技术增加了该领域中少数现有的下限技术。最后，该算法直接在 FPGA 上进行编码，优于最佳的加法器树。这项工作提出了另一种计数方式，这是求和的基础，它击败了大数的常规布尔电路，其中对大量数字求和是嵌入式系统（如神经网络和流媒体）中任何加速器的基础。^一种