Altering the performance of single transistors and integrated circuits at nominal operating conditions over time, as well as soft errors, are serious reliability issues for integrated CMOS circuits, especially when used in space applications. In principle, the effect of soft errors becomes even more critical if the circuit performance degrades over time. To address this detrimental behavior, the impact of performance degradation due to NBTI on the soft error susceptibility of integrated circuits is analyzed thoroughly. For this, we analyze the critical charge sensitivity of the two‐input NAND gate and NOR gate for different operating temperatures at stress times up to 3 years. The results show that the critical charge decreases with the temperature and strongly depends on the input states. Next, we validate the results employing the c17 ISCAS'85 benchmark suite, employing the PTM model with the HSPICE to estimate the soft error at the sensitive nodes. The critical charge is observed to be sensitive to the selected supply voltage and device temperature and thus provides a good measure for the soft error susceptibility with respect to NBTI at various operation conditions.

中文翻译：

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负偏置温度不稳定性对定标逻辑电路中单事件瞬变的影响

随着时间的推移，在正常工作条件下改变单个晶体管和集成电路的性能以及软错误是集成电路CMOS严重的可靠性问题，尤其是在空间应用中。原则上，如果电路性能随时间下降，则软错误的影响变得更加关键。为了解决这种有害行为，对由于NBTI而导致的性能下降对集成电路的软错误敏感性的影响进行了详尽的分析。为此，我们分析了在高达3年的应力时间下，不同工作温度下的双输入NAND门和NOR门的临界电荷敏感性。结果表明，临界电荷随温度而降低，并且在很大程度上取决于输入状态。接下来，我们使用c17 ISCAS'验证结果 85个基准测试套件，采用带有HSPICE的PTM模型来估计敏感节点处的软错误。观察到临界电荷对选定的电源电压和器件温度敏感，因此可以很好地衡量各种操作条件下相对于NBTI的软错误敏感性。