The deep learning has become the key for artificial intelligence applications development. It was successfully used to solve computer vision tasks. But the deep learning algorithms are based on Deep Neural Networks (DNN) with many hidden layers which need a huge computation effort and a big storage space. Thus, the general-purpose graphical processing units (GPGPU) are the best candidate for DNN development and inference because of their high number of processing core and the big integrated memory. In the other side, the disadvantage of the GPGPU is high-power consumption. In a real-world application, the processing unit is an embedded system based on limited power and computation resources. In recent years, Field Programmable Gate Array (FPGA) becomes a serious solution that can outperform GPGPU because of their flexible architecture and low power consumption. The FPGA is equipped with a very small integrated memory and a low bandwidth. To make DNNs fit into FPGA we need a lot of optimization techniques at different levels such as the network level, the hardware level, and the implementation tools level. In this paper, we will cite the existing optimization techniques and evaluate them to provide a complete overview of FPGA based DNN accelerators.

深度学习已成为人工智能应用程序开发的关键。它已成功用于解决计算机视觉任务。但是深度学习算法基于具有许多隐藏层的深度神经网络（DNN），需要大量的计算工作和大量的存储空间。因此，由于通用图形处理单元（GPGPU）的处理核心数量众多且集成内存很大，因此是DNN开发和推理的最佳选择。另一方面，GPGPU的缺点是功耗高。在实际应用中，处理单元是基于有限功能和计算资源的嵌入式系统。最近几年，现场可编程门阵列（FPGA）成为一种严肃的解决方案，因为其灵活的体系结构和低功耗，其性能可超越GPGPU。FPGA配备了非常小的集成存储器和低带宽。为了使DNN适合FPGA，我们需要在不同级别（例如网络级别，硬件级别和实现工具级别）使用许多优化技术。在本文中，我们将引用现有的优化技术并对它们进行评估，以提供基于FPGA的DNN加速器的完整概述。